Abstract: A fractional-n clock generator includes a first digital delay line module, a second delay line module, an address generator and a selector. The first delay line module receives a frequency-divided clock signal and generates first delay signals having different phase differences with respect to the clock signal. The second delay line module receives the clock signal and generates second delay signals having different phase differences with respect to the clock signal. The address generator selects one of the first delay signals as an output signal of the first delay line module and one of the second delay signals as an output signal of the second delay line module. The selector selects one of the output signals of the first delay line module and the second delay line module as an output signal. A delay of the first delay line module is different from that of the second delay line module.