Abstract: A memory circuit includes a memory cell, a data line configured to be coupled with the memory cell, a node, a precharge circuit, a first transistor of a first type, and a second transistor of the first type. The precharge circuit is configured to charge the node toward a predetermined voltage level. The first transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the first transistor has a first threshold voltage. The second transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the second transistor having a second threshold voltage different from the first threshold voltage.

Abstract: An electronic device includes a first circuit, and a delay circuit electrically connected to the first circuit. The delay circuit includes a resistor, a capacitor, and a process, voltage or temperature (PVT) compensation circuit electrically connected to the capacitor.

Abstract: A memory circuit includes a memory cell, a data line configured to be coupled with the memory cell, a node, a precharge circuit, a first transistor of a first type, and a second transistor of the first type. The precharge circuit is configured to charge the node toward a predetermined voltage level. The first transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the first transistor has a first threshold voltage. The second transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the second transistor having a second threshold voltage different from the first threshold voltage.

Abstract: An electronic device includes a first circuit, and a delay circuit electrically connected to the first circuit. The delay circuit includes a resistor, a capacitor, and a process, voltage or temperature (PVT) compensation circuit electrically connected to the capacitor.

Abstract: A memory circuit includes a memory cell, a data line coupled to the memory cell, a sense amplifier having an input terminal, a precharge circuit coupled to the input terminal of the sense amplifier, a first transistor of a first type, and a second transistor of the first type. The first transistor is coupled between the input terminal of the sense amplifier and the data line, and the second transistor is coupled between to the input terminal of the sense amplifier and the data line. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage lower than the first threshold voltage.

Abstract: A memory circuit includes a memory cell, a data line coupled to the memory cell, a sense amplifier having an input terminal, a precharge circuit coupled to the input terminal of the sense amplifier, a first transistor of a first type, and a second transistor of the first type. The first transistor is coupled between the input terminal of the sense amplifier and the data line, and the second transistor is coupled between to the input terminal of the sense amplifier and the data line. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage lower than the first threshold voltage.

Abstract: A semiconductor device is provided to have two groups of nonvolatile memory cells, two groups of data registers and a compare circuit. Each of the two groups of the nonvolatile memory cells stores a set of predetermined data and a set of complementary data respectively. The two groups of data registers are respectively connected to the two groups of the nonvolatile memory cells. The compare circuit is connected to the two groups of the data registers, for performing a comparison to generate a compare result.

Abstract: A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading, erase or programming operations. A power-on control circuit controls the operation of the information array.

Abstract: A semiconductor device is provided to have two groups of nonvolatile memory cells, two groups of data registers and a compare circuit. Each of the two groups of the nonvolatile memory cells stores a set of predetermined data and a set of complementary data respectively. The two groups of data registers are respectively connected to the two groups of the nonvolatile memory cells. The compare circuit is connected to the two groups of the data registers, for performing a comparison to generate a compare result.

Abstract: A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading, erase or programming operations. A power-on control circuit controls the operation of the information array.

Abstract: A read reference determining the logical value for results read from memory is adjusted during unstable power conditions.

Abstract: A read reference determining the logical value for results read from memory is adjusted during unstable power conditions.

Abstract: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and loading nonvolatile memory data and nonvolatile memory complementary data to a read data register and a read complementary data register, respectively. The nonvolatile memory data and the nonvolatile memory complementary data are compared with the read data register and the read complementary data register during the power on sequence, e.g., after initial power up or power on reset (POR). When the comparison determines a mismatch, the loading of the nonvolatile memory data and the nonvolatile memory complementary data to the read data register and the read complementary data register, respectively, is repeated.

Abstract: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and loading nonvolatile memory data and nonvolatile memory complementary data to a read data register and a read complementary data register, respectively. The nonvolatile memory data and the nonvolatile memory complementary data are compared with the read data register and the read complementary data register during the power on sequence, e.g., after initial power up or power on reset (POR). When the comparison determines a mismatch, the loading of the nonvolatile memory data and the nonvolatile memory complementary data to the read data register and the read complementary data register, respectively, is repeated.

Abstract: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and performing an error bit check on at least one memory cell in the flash memory during initial power up. The at least one memory cell in the flash memory is read only after the error bit check determines that the device voltage is stable. The data read from the at least one memory cell is loaded to an information register.

Abstract: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and performing an error bit check on at least one memory cell in the flash memory during initial power up. The at least one memory cell in the flash memory is read only after the error bit check determines that the device voltage is stable. The data read from the at least one memory cell is loaded to an information register.