Patents by Inventor Chouki Aktouf

Chouki Aktouf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8010918
    Abstract: The invention relates to a method comprising the following steps: HDL instruction sequences which are to be at the origin of memory elements during the synthesis of the system are automatically localized in the original HDL description files; and so-called SCAN HDL instructions are inserted into at least some of the HDL description files in an automatic sequential manner and without relational or functional analysis of the identified memory elements, ensuring that at least one so-called SCAN channel is obtained during the synthesis of the system, linking the memory elements.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: August 30, 2011
    Assignee: Institut National Polytechnique de Grenoble
    Inventor: Chouki Aktouf
  • Patent number: 7725784
    Abstract: The present invention relates to the testing of functional or IP cores forming part of a system on chip, SoC. The invention is implemented using a testing means and a communication means to test at least one functional or IP core. The testing means comprises a wrapper in which the core is embedded, this wrapper implements preferably the IEEE P1500 standard architecture but can also implement other standard architectures. The testing means can be extended to a Simple Network Management Protocol, SNMP, the widely adopted TCP/IP management protocol. The communication means comprises a test bus connected to the communication network. The proxy agent can implement the SNMP protocol, among others.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: May 25, 2010
    Assignee: Institut National Polytechnique de Grenoble
    Inventors: Oussama Laouamri, Chouki Aktouf
  • Publication number: 20080295045
    Abstract: The invention relates to a method comprising the following steps: HDL instruction sequences which are to be at the origin of memory elements during the synthesis of the system are automatically localised in the original HDL description files; and so-called SCAN HDL instructions are inserted into at least some of the HDL description files in an automatic sequential manner and without relational or functional analysis of the identified memory elements, ensuring that at least one so-called SCAN channel is obtained during the synthesis of the system, linking the memory elements.
    Type: Application
    Filed: February 11, 2005
    Publication date: November 27, 2008
    Inventor: Chouki Aktouf
  • Publication number: 20080034334
    Abstract: The present invention relates to the testing of functional or IP cores forming part of a system on chip, SoC. The invention is implemented using a testing means and a communication means to test at least one functional or IP core. The testing means comprises a wrapper in which the core is embedded, this wrapper implements preferably the IEEE P1500 standard architecture but can also implement other standard architectures. The testing means can be extended to a Simple Network Management Protocol, SNMP, the widely adopted TCP/IP management protocol. The communication means comprises a test bus connected to the communication network. The proxy agent can implement the SNMP protocol, among others.
    Type: Application
    Filed: February 17, 2005
    Publication date: February 7, 2008
    Inventors: Oussama Laouamri, Chouki Aktouf