Patents by Inventor Choung Sik SONG

Choung Sik SONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200144289
    Abstract: Provided herein is a semiconductor device and a method of manufacturing the same. The method includes alternately forming sacrificial layers and interlayer insulating layers on a semiconductor substrate. The method further includes forming a slit to expose the sacrificial layers by etching through the sacrificial layers and the interlayer insulating layers and forming interlayer openings by removing the exposed sacrificial layers. The method also includes depositing a conductive material in the interlayer openings and forming seams in which core patterns are deposited. The method additionally includes oxidizing a portion of the conductive material in the interlayer openings using a wet etching process and forming conductive patterns by removing the oxidized portion of the conductive material from the interlayer openings while leaving the seams intact.
    Type: Application
    Filed: January 3, 2020
    Publication date: May 7, 2020
    Applicant: SK hynix Inc.
    Inventors: Seung Cheol LEE, Woo Jae CHUNG, Choung Sik SONG
  • Patent number: 10573663
    Abstract: Provided herein is a semiconductor device and a method of manufacturing the same. The method includes alternately forming sacrificial layers and interlayer insulating layers on a semiconductor substrate. The method further includes forming a slit to expose the sacrificial layers by etching through the sacrificial layers and the interlayer insulating layers and forming interlayer openings by removing the exposed sacrificial layers. The method also includes depositing a conductive material in the interlayer openings and forming seams in which core patterns are deposited. The method additionally includes oxidizing a portion of the conductive material in the interlayer openings using a wet etching process and forming conductive patterns by removing the oxidized portion of the conductive material from the interlayer openings while leaving the seams intact.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: February 25, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung Cheol Lee, Woo Jae Chung, Choung sik Song
  • Publication number: 20190267395
    Abstract: Provided herein is a semiconductor device and a method of manufacturing the same. The method includes alternately forming sacrificial layers and interlayer insulating layers on a semiconductor substrate. The method further includes forming a slit to expose the sacrificial layers by etching through the sacrificial layers and the interlayer insulating layers and forming interlayer openings by removing the exposed sacrificial layers. The method also includes depositing a conductive material in the interlayer openings and forming seams in which core patterns are deposited. The method additionally includes oxidizing a portion of the conductive material in the interlayer openings using a wet etching process and forming conductive patterns by removing the oxidized portion of the conductive material from the interlayer openings while leaving the seams intact.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Applicant: SK hynix Inc.
    Inventors: Seung Cheol LEE, Woo Jae CHUNG, Choung Sik SONG
  • Patent number: 10332909
    Abstract: Provided herein is a semiconductor device and a method of manufacturing the same. The method includes alternately forming sacrificial layers and interlayer insulating layers on a semiconductor substrate. The method further includes forming a slit to expose the sacrificial layers by etching through the sacrificial layers and the interlayer insulating layers and forming interlayer openings by removing the exposed sacrificial layers. The method also includes depositing a conductive material in the interlayer openings and forming seams in which core patterns are deposited. The method additionally includes oxidizing a portion of the conductive material in the interlayer openings using a wet etching process and forming conductive patterns by removing the oxidized portion of the conductive material from the interlayer openings while leaving the seams intact.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 25, 2019
    Assignee: SK hynix Inc.
    Inventors: Seung Cheol Lee, Woo Jae Chung, Choung Sik Song
  • Publication number: 20190115360
    Abstract: Provided herein is a semiconductor device and a method of manufacturing the same. The method includes alternately forming sacrificial layers and interlayer insulating layers on a semiconductor substrate. The method further includes forming a slit to expose the sacrificial layers by etching through the sacrificial layers and the interlayer insulating layers and forming interlayer openings by removing the exposed sacrificial layers. The method also includes depositing a conductive material in the interlayer openings and forming seams in which core patterns are deposited. The method additionally includes oxidizing a portion of the conductive material in the interlayer openings using a wet etching process and forming conductive patterns by removing the oxidized portion of the conductive material from the interlayer openings while leaving the seams intact.
    Type: Application
    Filed: May 22, 2018
    Publication date: April 18, 2019
    Applicant: SK hynix Inc.
    Inventors: Seung Cheol LEE, Woo Jae CHUNG, Choung Sik SONG