Patents by Inventor Chris A. Nauert

Chris A. Nauert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8232209
    Abstract: A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: July 31, 2012
    Assignee: Spansion LLC
    Inventors: Christopher E. Brannon, Michael Wedlake, Chris A. Nauert
  • Publication number: 20110136268
    Abstract: A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.
    Type: Application
    Filed: February 11, 2011
    Publication date: June 9, 2011
    Applicant: SPANSION LLC
    Inventors: Christopher E. Brannon, Michael Wedlake, Chris A. Nauert
  • Patent number: 7915169
    Abstract: A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: March 29, 2011
    Assignee: Spansion LLC
    Inventors: Christopher E. Brannon, Michael Wedlake, Chris A. Nauert
  • Publication number: 20090117734
    Abstract: A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.
    Type: Application
    Filed: November 2, 2007
    Publication date: May 7, 2009
    Applicant: SPANSION LLC
    Inventors: Christopher E. Brannon, Michael Wedlake, Chris A. Nauert
  • Publication number: 20080157289
    Abstract: A method of processing a semiconductor structure is provided. The method includes forming a polish stop layer over one or more features on a substrate; forming a first dielectric layer over the polish stop layer, a valley portion of the first dielectric layer being just above a top of the polish stop layer; and polishing the dielectric layer down to the top of the polish stop layer. By forming a just enough dielectric layer to allow gap-fill on the substrate and polishing the dielectric layer down to the top of the polish stop layer, the method can reduce the cost and controls associated with forming the first dielectric layer.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Applicant: SPANSION LLC
    Inventors: Chris A. Nauert, Kelley Kyle Higgins, Sr.
  • Patent number: 6046796
    Abstract: In a semiconductor process which utilizes a plasma within a process tool chamber, a method of using optical emission spectroscopy (OES) to monitor a particular parameter of the process is disclosed. A first wavelength present in the plasma is determined which varies highly in intensity depending on the particular parameter by observing a statistically significant sample representing variations of the particular parameter. A second wavelength of chemical significance to the process is also determined which is relatively stable in intensity over time irrespective of variations of the particular parameter, also by observing a statistically significant sample representing variations of the particular parameter. These two wavelengths may be determined from test wafers and off-line physical measurements.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: April 4, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Markle, Michael J. Gatto, Chris A. Nauert, Yi Cheng, Richard B. Patty