Abstract: Storage circuitry is provided, that is designed to form part of a memory hierarchy. The storage circuitry comprises receiver circuitry for receiving a request to obtain data from the memory hierarchy. Transfer circuitry causes the data to be stored at a selected destination in response to the request, wherein the selected destination is selected in dependence on at least one selection condition. Tracker circuitry tracks the request while the request is unresolved. If at least one selection condition is met then the destination is the storage circuitry and otherwise the destination is other storage circuitry in the memory hierarchy.

Abstract: An apparatus has processing circuitry, register rename circuitry and control circuitry which selects one of first and second move handling techniques for handling a move instruction specifying a source logical register and a destination logical register. In the first technique, the register rename circuitry maps the destination logical register of the move to the same physical register as the source logical register. In the second technique, the processing circuitry writes a data value read from a physical register corresponding to the source logical register to a different physical register corresponding to the destination local register. The second technique is selected when the move instruction specifies the same source logical register as one of the source and destination logical registers as an earlier move instruction handled according to the first technique, and the register mapping used for that register when handling the earlier move instruction is still current.

Abstract: Arbitration circuitry is provided for arbitrating between requests awaiting servicing. The requests require variable numbers of resources and the arbitration circuitry permits the request to be serviced in a different order to the order in which they were received. Checking circuitry prevents a given request other than a oldest request from being serviced when a number of available resources is less than a threshold number of resources. The threshold number is varied based on the number of resources required for at least one other request awaiting servicing.

Abstract: There is provided a data processing apparatus that includes processing circuitry for executing a plurality of instructions. Storage circuitry stores a plurality of entries, each entry relating to an instruction in the plurality of instructions and including a dependency field. The dependency field stores a data dependency of that instruction on a previous instruction in the plurality of instructions. Scheduling circuitry schedules the execution of the plurality of instructions in an order that depends on each data dependency. When the previous instruction is a single-cycle instruction, the dependency field includes a reference to one of the entries that relates to the previous instruction, otherwise, the data dependency field includes an indication of an output destination of the previous instruction.

Abstract: An apparatus has processing circuitry, register rename circuitry and control circuitry which selects one of first and second move handling techniques for handling a move instruction specifying a source logical register and a destination logical register. In the first technique, the register rename circuitry maps the destination logical register of the move to the same physical register as the source logical register. In the second technique, the processing circuitry writes a data value read from a physical register corresponding to the source logical register to a different physical register corresponding to the destination local register. The second technique is selected when the move instruction specifies the same source logical register as one of the source and destination logical registers as an earlier move instruction handled according to the first technique, and the register mapping used for that register when handling the earlier move instruction is still current.

Abstract: Arbitration circuitry is provided for arbitrating between requests awaiting servicing. The requests require variable numbers of resources and the arbitration circuitry permits the request to be serviced in a different order to the order in which they were received. Checking circuitry prevents a given request other than a oldest request from being serviced when a number of available resources is less than a threshold number of resources. The threshold number is varied based on the number of resources required for at least one other request awaiting servicing.

Abstract: A single threaded out-of-order processor 2 includes an architected register file 22 and a speculative register file 20. Speculative register allocation circuitry 24 serves to allocate speculative registers for use in accordance with an allocation sequence and taken from a position determined by a tail point. Read suppression circuitry 30 serves to maintain a boundary pointer corresponding to a position within the allocation sequence such that no speculative register more recently allocated within the allocation sequence than that corresponding to the boundary pointer can have a valid register value. The read suppression circuitry 30 serves to suppress read operations for source operands lying within a read-suppression region delimited by the tail point and the boundary pointer. Separate boundary pointers may be maintained for different types of register values, such as integer register values and floating point register values.

Abstract: A single threaded out-of-order processor 2 includes an architected register file 22 and a speculative register file 20. Speculative register allocation circuitry 24 serves to allocate speculative registers for use in accordance with an allocation sequence and taken from a position determined by a tail point. Read suppression circuitry 30 serves to maintain a boundary pointer corresponding to a position within the allocation sequence such that no speculative register more recently allocated within the allocation sequence than that corresponding to the boundary pointer can have a valid register value. The read suppression circuitry 30 serves to suppress read operations for source operands lying within a read-suppression region delimited by the tail point and the boundary pointer. Separate boundary pointers may be maintained for different types of register values, such as integer register values and floating point register values.

Abstract: A method and apparatus for updating global branch history information are disclosed. A dynamic branch predictor within a data processing system includes a global branch history (GBH) buffer and a branch history table. The GBH buffer contains GBH information of a group of the most recent branch instructions. The branch history table includes multiple entries, each entry is associated with one or more branch instructions. The GBH information from the GBH buffer can be used to index into the branch history table to obtain a branch prediction signal. In response to a fetch group of instructions, a fixed number of GBH bits is shifted into the GBH buffer. The number of GBH bits is the same regardless of the number of branch instructions within the fetch group of instructions. In addition, there is a unique bit pattern associated with the case of no taken branch in the fetch group, regardless of the number of not-taken branches of even if there are any branches in the fetch group.