Patents by Inventor Chris Althouse

Chris Althouse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Class queue for network data switch to identify data memory locations by arrival time
    Patent number: 7996604
    Abstract: A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: August 9, 2011
    Assignee: Xilinx, Inc.
    Inventors: Gautam Nag Kavipurapu, Sweatha Rao, Chris Althouse
  • Striping of data into memory of a network data switch to prevent read and write collisions
    Patent number: 7730276
    Abstract: A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: June 1, 2010
    Assignee: XILINX, Inc.
    Inventors: Gautam Nag Kavipurapu, Sweatha Rao, Chris Althouse
  • Time based data storage for shared network memory switch
    Patent number: 7568074
    Abstract: A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: July 28, 2009
    Assignee: XILINX, Inc.
    Inventors: Gautam Nag Kavipurapu, Sweatha Rao, Chris Althouse
  • Scalable shared network memory switch for an FPGA
    Patent number: 7439763
    Abstract: A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: October 21, 2008
    Assignee: Xilinx, Inc.
    Inventors: Gautam Nag Kavipurapu, Sweatha Rao, Chris Althouse