Abstract: A system can create a first graph that represents first values of current configurations of a computer hardware as first nodes and first dependencies of the current configurations as first links. The system can create first embedding vectors based on the first graph. The system can input the first embedding vectors to a graph isomorphism network to produce modified first embedding vectors. The system can identify specified configurations for the computer hardware. The system can create a second graph that represents second values of the specified configurations. The system can create second embedding vectors based on the second graph. The system can input the second embedding vectors to the graph isomorphism network to produce modified second embedding vectors. The system can perform a graph isomorphism evaluation on the modified first embedding vectors and the modified second embedding vectors to determine an amount of difference.

Abstract: A system can create a first graph that represents first values of current configurations of a computer hardware as first nodes and first dependencies of the current configurations as first links. The system can create first embedding vectors based on the first graph. The system can input the first embedding vectors to a graph isomorphism network to produce modified first embedding vectors. The system can identify specified configurations for the computer hardware. The system can create a second graph that represents second values of the specified configurations. The system can create second embedding vectors based on the second graph. The system can input the second embedding vectors to the graph isomorphism network to produce modified second embedding vectors. The system can perform a graph isomorphism evaluation on the modified first embedding vectors and the modified second embedding vectors to determine an amount of difference.

Abstract: A subsea connector includes a recess arranged on an inner surface of the housing of the subsea connector. The recess is configured to receive a canted coil spring such that it provides an electrical multi-point contact between an outer shielding layer, sometimes referred to as a screen, of a subsea cable. The subsea connector further includes a link configured to releasably attach an earth link wire to the housing.

Abstract: A subsea connector includes a recess arranged on an inner surface of the housing of the subsea connector. The recess is configured to receive a canted coil spring such that it provides an electrical multi-point contact between an outer shielding layer, sometimes referred to as a screen, of a subsea cable. The subsea connector further includes a link configured to releasably attach an earth link wire to the housing.

Abstract: A mobile device including a positioning device for determining position by timing analysis of received signals, the positioning device including a system for determining timing accuracy, the system including first signal generating means for continuously generating a first clock signal whilst the positioning device is inactive, second signal generating means for discontinuously generating a second clock signal during a plurality of spaced apart time periods, and accuracy determining means for determining the accuracy of the first clock signal using timing data from the second clock signal, the positioning device being arranged to determine position by use of the determined timing accuracy of the first clock.

Abstract: A mobile device including a positioning device for determining position by timing analysis of received signals, the positioning device including a system for determining timing accuracy, the system including first signal generating means for continuously generating a first clock signal whilst the positioning device is inactive, second signal generating means for discontinuously generating a second clock signal during a plurality of spaced apart time periods, and accuracy determining means for determining the accuracy of the first clock signal using timing data from the second clock signal, the positioning device being arranged to determine position by use of the determined timing accuracy of the first clock.

Abstract: A system and methods are described for the evaluation of the integrity of a wafer cassette and the disposition thereof based upon evaluation of wafer measurement data obtained using a wafer sorter cassette mapping system utilized in-line during wafer sorting operations. One method comprises initially placing two or more wafers into two or more of a plurality of slots in the wafer cassette. A wafer sorter cassette mapping sensor affixed to the wafer sorter is then scanned over the two or more wafers in the slots of the wafer cassette, using a wafer sorter. The positions of the wafers in the wafer cassette are then measured while scanning the sensor over the wafers. The wafer position measurements are then evaluated using a modeling system to determine slot positions within the cassette associated with the wafer position measurements, and a determination of the integrity of the cassette is generated based on the slot position determinations.

Abstract: According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a photoresist layer on a surface of a wafer. The wafer includes an array of die that includes a plurality of complete die and at least one partial edge die. The wafer has an edge that has a substantially rounded profile causing undersized patterns in semiconductor devices formed on partial edge die. A first exposure intensity is assigned to a first group of die on the surface of the wafer. The first group of die includes a group of complete die, and the first exposure intensity is assigned based at least in part on the location of the first group of die on the surface of the wafer. A second exposure intensity is assigned to a second group of die on the surface of the wafer. The second group of die includes at least one partial edge die. The second exposure intensity less than the first exposure intensity to compensate for reduced line width due to the wafer edge topography.