Patents by Inventor Chris B. Wilkerson

Chris B. Wilkerson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7624258
    Abstract: Associated with an instruction in a program is a computation history. The computation history represents all objects that affect the result of the instruction, such objects including (but not limited to) registers, memory locations, static values, and instruction program counters. The computation history may be used to make a prediction about a property of the instruction.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: November 24, 2009
    Assignee: Intel Corporation
    Inventors: Chris B. Wilkerson, Jared W. Stark, Renju Thomas
  • Patent number: 7143272
    Abstract: Associated with an instruction in a program is a computation history. The computation history represents all objects that affect the result of the instruction, such objects including (but not limited to) registers, memory locations, static values, and instruction program counters. The computation history may be used to make a prediction about a property of the instruction.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: November 28, 2006
    Assignee: Intel Corporation
    Inventors: Chris B. Wilkerson, Jared W. Stark, Renju Thomas
  • Publication number: 20040128490
    Abstract: Associated with an instruction in a program is a computation history. The computation history represents all objects that affect the result of the instruction, such objects including (but not limited to) registers, memory locations, static values, and instruction program counters. The computation history may be used to make a prediction about a property of the instruction.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 1, 2004
    Inventors: Chris B. Wilkerson, Jared W. Stark, Renju Thomas
  • Publication number: 20040128448
    Abstract: Processor architectures, and in particular, processor architectures with a cache-like structure to enable memory communication during runahead execution. In accordance with an embodiment of the present invention, a system including a memory; and an out-of-order processor coupled to the memory. The out-of-order processor including at least one execution unit, at least one cache coupled to the at least one execution unit; at least one address source coupled to the at least one cache; and a runahead cache coupled to the at least one address source.
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Applicant: INTEL CORPORATION
    Inventors: Jared W. Stark, Chris B. Wilkerson, Onur Mutlu
  • Publication number: 20030122865
    Abstract: Methods and apparatuses to view information include, ordering a list of information content segments that have previously appeared on a web page, wherein the web page is displayed in a first area of an information display and displaying the list of information content segments to be viewed concurrently with the web page.
    Type: Application
    Filed: January 3, 2002
    Publication date: July 3, 2003
    Inventors: Adam T. Lake, Carl S. Marshall, Chris B. Wilkerson