Abstract: A data alignment system suitable for use in manipulating the positioning of a designated portion of a data stream transmitted by a high speed communications system, so as to facilitate further processing of the data carried by the data stream. The data alignment system includes a detector and an alignment component in communication with each other. In operation, the detector locates and identifies, in accordance with suitable instructions, the designated portion of the data stream. The alignment component then repositions, in accordance with suitable instructions, the designated portion of the data stream at a predetermined location within the data stream.

Abstract: A data alignment system suitable for use in manipulating the positioning of a designated portion of a data stream transmitted by a high speed communications system, so as to facilitate further processing of the data carried by the data stream. The data alignment system includes a detector and an alignment component in communication with each other. In operation, the detector locates and identifies, in accordance with suitable instructions, the designated portion of the data stream. The alignment component then repositions, in accordance with suitable instructions, the designated portion of the data stream at a predetermined location within the data stream.

Abstract: A system and method for enabling a programmable device to execute instructions without interruption. An instruction space for storing instructions from a host application is bifurcated to define a program segment and a hold segment. At startup, instructions are loaded into the hold segment, and the programmable device begins executing those instructions. While the hold segment instructions are executed, the program segment is loaded with instructions. Once the program segment is filled, control is shifted to it and instructions from this segment are executed by the programmable device. When the program segment has been executed, control is shifted back to the hold segment, and instructions are taken from it while the program segment is reloaded with a fresh set of instructions from the host application. Once the program segment is reloaded, control is redirected and execution of instructions from the program segment is continued.

Abstract: An bit error rate tester for use in connection with a high speed networks. The bit error rate tester includes transmit and receive ports, as well as a sequence generator, memory, synchronizer, sequence start detect module, and comparator. The sequence generator generates a bit sequence for transmission through a network path. The bit sequence returns to the bit error rate tester by way of the receive port. The synchronizer then bit-aligns the received bit sequence to compensate for idles/fill words added/dropped as the bit sequence transited the network. The synchronized bit sequence is passed to the start word detector which detects start and end words in the bit sequence and instructs the comparator to compare only data between the start and end words. The comparator compares the received bit sequence with a copy of the transmitted bit sequence regenerated from the memory, and calculates a bit error rate.

Abstract: An bit error rate tester for use in connection with a high speed networks. The bit error rate tester includes transmit and receive ports, as well as a sequence generator, memory, synchronizer, sequence start detect module, and comparator. The sequence generator generates a bit sequence for transmission through a network path. The bit sequence returns to the bit error rate tester by way of the receive port. The synchronizer then bit-aligns the received bit sequence to compensate for idles/fill words added/dropped as the bit sequence transited the network. The synchronized bit sequence is passed to the start word detector which detects start and end words in the bit sequence and instructs the comparator to compare only data between the start and end words. The comparator compares the received bit sequence with a copy of the transmitted bit sequence regenerated from the memory, and calculates a bit error rate.

Abstract: Systems and methods for altering a latency of network messages. A latency control system is configured to alter the latency of one or more network messages transmitted in a network. The latency of the network messages may simulate a latency associated with a network connection. A message queue is controlled by the latency control system to implement the latency, which can be increased or decreased. The latency may be increased and/or decreased dynamically.

Abstract: A modification subsystem suitable for introducing user-defined errors into a designated data unit substantially in real time, so as to facilitate evaluation of the response of a high speed data communications system to errors as such are exemplified in the modified data unit. The modification subsystem includes a modification logic and state machine that communicates with a command stack memory and one or more jamming mode registers. Upon locating and identifying the designated data unit in a data stream, the modification logic and state machine accesses a jam setting stored in a jam mode register and, if it is determined that the modification that corresponds to the jam setting is valid, modifies the designated data unit in accordance with the jam setting. If the proposed modification is invalid, the modification is aborted.