Abstract: Methods and systems to reduce clock spurs produced by a direct-RF modular to acceptable levels using a digital predistortion compensation signal. The digital compensation signal may be used to generate a sine wave in the digital domain with adjustable phase and amplitude. The digital compensation signal may be added to a digital signal processor (DSP) section of an upconvertor, and may be combined with the undesired clock spur signal to reduce it or even cancel it out completely. In some implementations, the digital predistortion compensation signal may have a similar level of the clock spur such that when added to the clock spur, results in a clock spur having a reduced amplitude.