Patents by Inventor Chris Cureton

Chris Cureton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for forming deep silicon via for grounding of circuits and devices, emitter ballasting and isolation
    Patent number: 9105681
    Abstract: According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: August 11, 2015
    Assignee: Newport Fab, LLC
    Inventors: Volker Blaschke, Todd Thibeault, Chris Cureton, Paul Hurwitz, Arjun Kar-Roy, David Howard, Marco Racanelli
  • Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation
    Patent number: 8598713
    Abstract: According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: December 3, 2013
    Assignee: Newport Fab, LLC
    Inventors: Volker Blaschke, Todd Thibeault, Chris Cureton, Paul Hurwitz, Arjun Kar-Roy, David Howard, Marco Racanelli
  • Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation
    Publication number: 20110018109
    Abstract: According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.
    Type: Application
    Filed: May 20, 2010
    Publication date: January 27, 2011
    Applicant: NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR
    Inventors: Volker Blaschke, Todd Thibeault, Chris Cureton, Paul Hurwitz, Arjun Kar-Roy, David Howard, Marco Racanelli