Abstract: A command is received to place a first physical machine into a lower power mode. The first physical machine has a virtual machine. In response to the received command, a procedure is performed to migrate the virtual machine from the first physical machine to a second physical machine.

Abstract: A system has plural physical machines that contain virtual machines. A load balancer receives a request from a client. In response to the request, it is determined whether at least one additional virtual machine should be started up. In response to determining that at least one additional virtual machine should be started up, the load balancer sends at least one command to start up the at least one additional virtual machine in at least one of the physical machines.

Abstract: A combined-hardware-and-software secure-platform interface to which operating systems and customized control programs interface within a computer system. The combined-hardware-and-software secure-platform interface employs a hardware platform that provides at least four privilege levels, non-privileged instructions, non-privileged registers, privileged instructions, privileged registers, and firmware interfaces. The combined-hardware-and-software secure-platform interface conceals all privileged instructions, privileged registers, and firmware interfaces and privileged registers from direct access by operating systems and custom control programs, providing to the operating systems and custom control programs the non-privileged instructions and non-privileged registers provided by the hardware platform as well as a set of callable software services.

Abstract: A method and system for nearly immediately trapping a failure-to-check-a-return-value error in a computer program. Modern processor architectures, such as the Intel® IA-64 processor architecture, provide for control speculation of load instructions, including 1-bit NAT registers, associated with general registers, that indicate occurrences of deferred exceptions arising during execution of control-speculative load instructions targeting the corresponding general registers. One embodiment of the present invention employs the NAT registers associated with general-purpose registers to distinguish special values, often indicating error conditions, stored in general-purpose registers serving to store the return values of functions and routines.

Abstract: A method and system for nearly immediately trapping a failure-to-check-a-return-value error in a computer program. Modern processor architectures, such as the Intel® IA-64 processor architecture, provide for control speculation of load instructions, including 1-bit NAT registers, associated with general registers, that indicate occurrences of deferred exceptions arising during execution of control-speculative load instructions targeting the corresponding general registers. One embodiment of the present invention employs the NAT registers associated with general-purpose registers to distinguish special values, often indicating error conditions, stored in general-purpose registers serving to store the return values of functions and routines.

Abstract: A computer apparatus for creating a trusted environment comprising a trusted device arranged to acquire a first integrity metric to allow determination as to whether the computer apparatus is operating in a trusted manner; a processor arranged to allow execution of a first trust routine and associated first operating environment, and means for restricting the first operating environment access to resources available to the trust routine, wherein the trust routine being arranged to acquire the first integrity metric and a second integrity metric to allow determination as to whether the first operating environment is operating in a trusted manner.

Abstract: A combined-hardware-and-software secure-platform interface to which operating systems and customized control programs interface within a computer system. The combined-hardware-and-software secure-platform interface employs a hardware platform that provides at least four privilege levels, non-privileged instructions, non-privileged registers, privileged instructions, privileged registers, and firmware interfaces. The combined-hardware-and-software secure-platform interface conceals all privileged instructions, privileged registers, and firmware interfaces and privileged registers from direct access by operating systems and custom control programs, providing to the operating systems and custom control programs the non-privileged instructions and non-privileged registers provided by the hardware platform as well as a set of callable software services.