Abstract: A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.

Abstract: Power consumption of an address bus interface is reduced by reducing drive duration of address signals on the address bus. The address bus interface may operate in normal or power saving mode. In power saving mode, address signals are driven for a quarter of a clock period instead of half a clock period and address strobe edges are moved so that they are aligned with valid address signals.

Abstract: A method and apparatus is described herein for serializing input data streams into an output data stream. A first and second input data stream are sampled upon rising edges of a first and second clocking signal, respectively, to reduce jitter from dependence on the falling edges of the clocking signals. The second clocking signal is 180 degrees out of phase with the first clocking signal to sample the first input data stream in the first unit interval of an output data stream and the second input data stream in the second unit interval of the output data stream. Consequently, a serialized output data stream is driven at twice the frequency of both the first and the second input data streams, including logical information from the first and second input data streams every period of the output data stream.

Abstract: Power consumption of an address bus interface is reduced by reducing drive duration of address signals on the address bus. The address bus interface may operate in normal or power saving mode. In power saving mode, address signals are driven for a quarter of a clock period instead of half a clock period and address strobe edges are moved so that they are aligned with valid address signals.

Abstract: Embodiments of the invention relate to a memory control hub (MCH) clock master of an MCH. Typically, in a computer system, a processor is coupled to the MCH by a front-side bus (FSB). Further, an input/output control hub (ICH) is typically coupled to the MCH by a back-side bus or Hub Link. In one embodiment, a host phase locked loop (HPLL) of the MCH clock master receives an FSB clock signal transmitted on the FSB and generates a local synchronous clock signal based upon the FSB clock signal. A delayed lock loop (DLL) of the MCH clock master also receives the FSB clock signal and generates a system clock signal. Particularly, the DLL synchronizes the system clock signal to the local synchronous clock and drives the system clock signal to many different devices on the board.

Abstract: Embodiments of the invention relate to a memory control hub (MCH) clock master of an MCH. Typically, in a computer system, a processor is coupled to the MCH by a front-side bus (FSB). Further, an input/output control hub (ICH) is typically coupled to the MCH by a back-side bus or Hub Link. In one embodiment, a host phase locked loop (HPLL) of the MCH clock master receives an FSB clock signal transmitted on the FSB and generates a local synchronous clock signal based upon the FSB clock signal. A delayed lock loop (DLL) of the MCH clock master also receives the FSB clock signal and generates a system clock signal. Particularly, the DLL synchronizes the system clock signal to the local synchronous clock and drives the system clock signal to many different devices on the board.