Abstract: A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state.

Abstract: A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memory determines if a task switch has occurred. If a task switch has not occurred, first-level cache memory sends the invalidated page table entry to a current running task directory. If a task switch has occurred, first-level cache memory loads from the second-level cache directory a collection of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve the collection of page table entries.

Abstract: Method and computer program product for recommending cost effective upgrades for a computer system. At least one performance parameter is determined for an existing computer system. Up to date performance specifications for available upgrade components are obtained. A variety of potential systems are modeled utilizing at least one upgrade component, and at least one component from the existing system to create upgrade scenarios. At least one performance parameter is predicted for each upgrade scenario. The performance parameters for the upgrade scenarios are compared to the performance parameters of the existing computer system. The cost-effectiveness is determined for each upgrade scenario, and upgrade recommendations are made when the cost-effectiveness meets or exceeds a target value.

Abstract: A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state.

Abstract: A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memory determines if a task switch has occurred. If a task switch has not occurred, first-level cache memory sends the invalidated page table entry to a current running task directory. If a task switch has occurred, first-level cache memory loads from the second-level cache directory a collection of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve the collection of page table entries.

Abstract: A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state.

Abstract: A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memory determines if a task switch has occurred. If a task switch has not occurred, first-level cache memory sends the invalidated page table entry to a current running task directory. If a task switch has occurred, first-level cache memory loads from the second-level cache directory a collection of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve the collection of page table entries.

Abstract: Method and computer program product for recommending cost effective upgrades for a computer system. At least one performance parameter is determined for an existing computer system. Up to date performance specifications for available upgrade components are obtained. A variety of potential systems are modeled utilizing at least one upgrade component, and at least one component from the existing system to create upgrade scenarios. At least one performance parameter is predicted for each upgrade scenario. The performance parameters for the upgrade scenarios are compared to the performance parameters of the existing computer system. The cost-effectiveness is determined for each upgrade scenario, and upgrade recommendations are made when the cost-effectiveness meets or exceeds a target value.

Abstract: A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state.

Abstract: A system and method for default data forwarding coherent caching agent is present. A node controller receives a cache line request from either a local caching agent (local processor) or from a remote node controller. When a node controller receives a request from a local caching agent, the node controller sends the corresponding cache line to the local caching agent, all the while maintaining cache line forward state control. When the node controller receives a request from a remote node controller, the node controller sends the cache line, along with the cache line forward state control, to the remote node controller. In addition, the node controller performs particular actions based upon the source of the cache line request, the request type, and the cache line current status.

Abstract: A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memory determines if a task switch has occurred. If a task switch has not occurred, first-level cache memory sends the invalidated page table entry to a current running task directory. If a task switch has occurred, first-level cache memory loads from the second-level cache directory a collection of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve the collection of page table entries.

Abstract: A method for operating a memory controller including receiving a current memory access request from an agent. A page management policy associated with the agent is determined in response to receiving the request. The memory controller is set to the page management policy associated with the agent and the current memory access request is executed on the memory controller. The results of the executing are transmitted to the agent.

Abstract: A cache for use in a memory controller, which processes data in a computer system having at least one processor, and a method for processing data utilizing a cache, are disclosed. The cache comprises a first array such as a tag array, a second array such as a data array, and a pointer for pointing to a portion of the second array that is associated with a portion of the first array, wherein the portion of the second array comprises the data to be processed, and wherein the number of times the at least one processor must undergo a first transfer latency is reduced. This is done by incorporating a prefetch mechanism within the cache. The computer system may include a plurality of processors with each data entry in the data array having an owner bit for each processor. The memory controller may also include a line preloader for prefetching data into the cache. Also, this design can be used in both single processor and multiprocessor systems.

Abstract: This disclosure relates to a method and apparatus for measuring the amount of time a personal computer system is powered on. A power on time (POT) routine is performed at a power on of the computer system. This routine sets up a timer to count the number of pre-selected time units (selected by a user) the system is powered on. The power on time count is stored in the PC's non-volatile memory. The routine sets an alarm field of the system's real time clock (RTC) to be activated after the pre-selected time unit has elapsed. A POT interrupt handler routine is installed in a chain for RTC interrupts and is invoked each time the alarm is activated (i.e., at each passage of the pre-selected time unit) while the system is powered on. When invoked, the POT interrupt handler routine increments the POT count and resets the RTC alarm to be activated after another pre-selected time unit has elapsed.

Abstract: A personal computer system includes a digital signal processor (DSP) subsystem that is connectable to a plurality of application specific hardware devices. A single DSP is operable under a DSP real-time operating system (RTOS) to concurrently handle a plurality of different signal processing functions on a real-time basis. A DSP data store is connected to the DSP and to the personal computer and includes addressable locations that emulate addressable I/O registers associated with the application specific hardware devices to enable the personal computer to run a plurality of application programs controlling operation of the hardware devices. Performance is enhanced for I/O read and write operations by delaying halting of the DSP allowing such operations to complete in a cycle during which the DSP is not accessing the data store.