Abstract: A system and method for architecting design for test circuitry (e.g., scan architecting) within an integrated circuit design having subdesigns (e.g., modules). The novel system contains a default operational mode (no user specification) and an operational mode based on user specifications; within either mode, the system recognizes and allows definition of subdesign scan chains which can be linked together alone or with other scan elements to architect complex scan chains (e.g., top level scan chains). The system includes specification, analysis, synthesis and reporting processes which can be used in an IC design having a hierarchical structure including modules. The specification process accesses a design database and a script file and allows a user to define global scan properties (scan style, number of chains, etc.), properties of a particular scan chain (membership, name, etc.), test signals (scan-in, scan-out, scan-enable, etc.

Abstract: A system and method for architecting design for test circuitry (e.g., scan architecting) within an integrated circuit design having subdesigns (e.g., modules). The novel system contains a default operational mode (no user specification) and an operational mode based on user specifications; within either mode, the system recognizes and allows definition of subdesign scan chains which can be linked together alone or with other scan elements to architect complex scan chains (e.g., top level scan chains). The system includes specification, analysis, synthesis and reporting processes which can be used in an IC design having a hierarchical structure including modules. The specification process accesses a design database and a script file and allows a user to define global scan properties (scan style, number of chains, etc.), properties of a particular scan chain (membership, name, etc.), test signals (scan-in, scan-out, scan-enable, etc.

Abstract: A computer implemented process and system for providing a scan insertion process having a reduced set of constraint driven compiler optimizations that provide an efficient and effective optimization for design for test implementations. The present invention includes a three tiered effort performance optimization process within a scan insertion process; a first tier operates to perform a set of optimizations (size design) only on elements of the design added for design for test (DFT). The second tier offers the first tier and performs the size design optimizations across all of the design while the third tier offers the second tier with sequential optimizations, circuit size downs, and another size design. Each higher user-selectable tier offers more complex optimizations and consumes additional processing time. An option to perform design constraints optimization (max fanout, max signal transition, and max capacitance) is also available.