Abstract: A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.

Abstract: A microprocessor embodies a poisoning technique with regard to load and store instructions that are related through a common memory reference. The microprocessor includes “store sets” that are created for loads and stores that share a common memory reference and that must execute in program order. The store sets include a value that points to a poison bit in a store set poison table that indicates whether a store instruction that is part of the store set is poisoned by a load instruction that prior to the store. If the store instruction is poisoned, a subsequent store set related load instruction will also be poisoned. That is, the present technique causes poison to propagate from a parent store to a subsequent memory reference dependent load using a store set.