Patents by Inventor Chris H. Simon

Chris H. Simon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8726498
    Abstract: The invention comprises methods for filling holes in printed wiring boards and printed wiring boards produced by these methods. The methods involve plating metal conductors inside the holes of the printed wiring boards while protecting the conducting surfaces of the printed wiring boards from being plated using photoresist film. The side surfaces of a printed wiring board are covered with photoresist. The photoresist is exposed to developing light, except the photoresist covering the holes on one side of the board is masked to prevent exposure of the holes to the developing light. The undeveloped photoresist covering the holes is removed. The board is subjected to a plating process, which deposits conductive materials in the holes, but the photoresist on the conducting surfaces of the board prevents conductive materials to be plated on the surfaces of the board.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: May 20, 2014
    Assignee: General Dynamics Advanced Information Systems
    Inventors: Deepak Keshav Pai, Chris H. Simon
  • Publication number: 20110067235
    Abstract: The invention comprises methods for filling holes in printed wiring boards and printed wiring boards produced by these methods. The methods involve plating metal conductors inside the holes of the printed wiring boards while protecting the conducting surfaces of the printed wiring boards from being plated using photoresist film. The side surfaces of a printed wiring board are covered with photoresist. The photoresist is exposed to developing light, except the photoresist covering the holes on one side of the board is masked to prevent exposure of the holes to the developing light. The undeveloped photoresist covering the holes is removed. The board is subjected to a plating process, which deposits conductive materials in the holes, but the photoresist on the conducting surfaces of the board prevents conductive materials to be plated on the surfaces of the board.
    Type: Application
    Filed: August 18, 2010
    Publication date: March 24, 2011
    Applicant: General Dynamics Advanced Information Systems, Inc
    Inventors: Deepak Keshav Pai, Chris H. Simon
  • Patent number: 7802360
    Abstract: The invention comprises methods for filling holes in printed wiring boards and printed wiring boards produced by these methods. The methods involve plating metal conductors inside the holes of the printed wiring boards while protecting the conducting surfaces of the printed wiring boards from being plated using photoresist film. The side surfaces of a printed wiring board are covered with photoresist. The photoresist is exposed to developing light, except the photoresist covering the holes on one side of the board is masked to prevent exposure of the holes to the developing light. The undeveloped photoresist covering the holes is removed. The board is subjected to a plating process, which deposits conductive materials in the holes, but the photoresist on the conducting surfaces of the board prevents conductive materials to be plated on the surfaces of the board.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: September 28, 2010
    Assignee: General Dynamics Advanced Information Systems, Inc.
    Inventors: Deepak Keshav Pai, Chris H. Simon
  • Patent number: 6621882
    Abstract: An apparatus and method for adjusting the clock delay in systems with multiple integrated circuits has a controller, a programmable clock generator and a plurality of integrated circuits, each integrated circuit including a data flip-flop, a programmable delay and a clock-fanout tree, wherein the clock delay in the integrated circuits is adjusted to match the inherent delay in the integrated circuit having the longest inherent delay.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: September 16, 2003
    Assignee: General Dynamics Information Systems, Inc.
    Inventors: Ronald R. Denny, Chris H. Simon, Joan E. Zak
  • Publication number: 20030026367
    Abstract: An apparatus and method for adjusting the clock delay in systems with multiple integrated circuits has a controller, a programmable clock generator and a plurality of integrated circuits, each integrated circuit including a data flip-flop, a programmable delay and a clock-fanout tree, wherein the clock delay in the integrated circuits is adjusted to match the inherent delay in the integrated circuit having the longest inherent delay.
    Type: Application
    Filed: March 2, 2001
    Publication date: February 6, 2003
    Inventors: Ronald R. Denny, Chris H. Simon, Joan E. Zak