Abstract: The claimed subject matter provides a system and/or a method that facilitates utilizing a resolution enhancement for a circuit feature. A scanning electron microscope component (104, 204, 304, 404) can provide at least one two-dimensional image of the circuit feature. An image analysis engine (106, 206, 306, 406) can analyze the two-dimensional image. An advanced process control (APC) engine (108, 208, 308, 408) can generate at least one instruction for at least one of a feed forward control and a feedback control and a process component (102, 202, 302, 402) can utilize the at least one instruction to minimize an error.

Abstract: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

Abstract: A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.

Abstract: A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.

Abstract: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

Abstract: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

Abstract: A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.

Abstract: A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules can be created to disallow layouts demonstrating poor manufacturability.

Abstract: For determining optimum optical proximity corrections (OPCs) for a mask pattern, mask areas are formed on a reticle with each mask area having the mask pattern of polygons that are modified with respective OPCs perturbations. A respective patterned area is fabricated on a semiconductor wafer from each mask area of the reticle. A respective microscopy image of each respective patterned area is generated to determine a respective error function for each mask area by comparing a desired image of the mask pattern and the respective microscopy image. The optimum OPCs are determined as the respective OPCs perturbations corresponding to one of the mask areas having the respective error function that is a minimum of the mask areas.

Abstract: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

Abstract: For determining optimum optical proximity corrections (OPCs) for a mask pattern, mask areas are formed on a reticle with each mask area having the mask pattern of polygons that are modified with respective OPCs perturbations. A respective patterned area is fabricated on a semiconductor wafer from each mask area of the reticle. A respective microscopy image of each respective patterned area is generated to determine a respective error function for each mask area by comparing a desired image of the mask pattern and the respective microscopy image. The optimum OPCs are determined as the respective OPCs perturbations corresponding to one of the mask areas having the respective error function that is a minimum of the mask areas.