Abstract: A method for controlling a refresh sequence for multiple memory elements within an electronic device is disclosed. The method involves adjusting a programmable signal delay to avoid a simultaneous memory refresh between two or more of the multiple memory elements and passing a refresh signal from one memory element to another memory element based on the programmable signal delay.

Abstract: An adaptive digital power control system is disclosed, which implements a digitally controlled, near real-time algorithm to accommodate multiple loop current mode controls for low voltage, high performance computing system power needs. For example, an adaptive digital power control system that is implemented with an FPGA to generate low voltages for high performance computing systems is disclosed, which includes a current and voltage loop compensation algorithm that enables the adaptive digital power control system to dynamically compensate for high current transients and EMI-related noise. The current and voltage loop compensation algorithm uses a combination of linear predictive coding and Kalman filtering techniques to provide dynamic current and voltage compensation, and implement a feed-forward technique using knowledge of the power system's output parameters to adequately adapt to the system's compensation needs.

Abstract: A method for controlling a refresh sequence for multiple memory elements within an electronic device is disclosed. The method involves adjusting a programmable signal delay to avoid a simultaneous memory refresh between two or more of the multiple memory elements and passing a refresh signal from one memory element to another memory element based on the programmable signal delay.

Abstract: An adaptive digital power control system is disclosed, which implements a digitally controlled, near real-time algorithm to accommodate multiple loop current mode controls for low voltage, high performance computing system power needs. For example, an adaptive digital power control system that is implemented with an FPGA to generate low voltages for high performance computing systems is disclosed, which includes a current and voltage loop compensation algorithm that enables the adaptive digital power control system to dynamically compensate for high current transients and EMI-related noise. The current and voltage loop compensation algorithm uses a combination of linear predictive coding and Kalman filtering techniques to provide dynamic current and voltage compensation, and implement a feed-forward technique using knowledge of the power system's output parameters to adequately adapt to the system's compensation needs.