Abstract: The present disclosure provides methods and systems for detecting small span loss changes in fiber optic networks. The present invention utilizes existing equipment without additional hardware to provide span loss measurements in a highly accurate manner. In an exemplary embodiment, the present invention utilizes power measurements associated with an optical supervisory channel (OSC) at both ends of a fiber span. These measurements are periodically sampled taking into account propagation delay along the fiber span. Further, these measurements are integrated or time-averaged to account for temporary fluctuations. The present invention can be utilized for intrusion detection (i.e., unwanted fiber taps), fiber degradation, and fiber aging performance. The present invention satisfies the criteria for a feasible (i.e., makes use of current architecture), cost-effective (i.e., does not require additional hardware), and highly accurate solution (i.e., capable of detecting span loss changes of 0.01 dB or 0.03%).

Abstract: The present disclosure provides methods and systems for detecting small span loss changes in fiber optic networks. The present invention utilizes existing equipment without additional hardware to provide span loss measurements in a highly accurate manner. In an exemplary embodiment, the present invention utilizes power measurements associated with an optical supervisory channel (OSC) at both ends of a fiber span. These measurements are periodically sampled taking into account propagation delay along the fiber span. Further, these measurements are integrated or time-averaged to account for temporary fluctuations. The present invention can be utilized for intrusion detection (i.e., unwanted fiber taps), fiber degradation, and fiber aging performance. The present invention satisfies the criteria for a feasible (i.e., makes use of current architecture), cost-effective (i.e., does not require additional hardware), and highly accurate solution (i.e., capable of detecting span loss changes of 0.01 dB or 0.03%).

Abstract: The incorporation of an aluminum arsenide (AlAs) buffer layer in a gallium arsenide (GaAs) field effect transistor (FET) structure is found to improve the overall device performance, particularly in the high temperature operating regime. Similar characteristics may be obtained from devices fabricated with an Al.sub.x Ga.sub.1-x As 0.2.ltoreq.x.ltoreq.1 barrier layer. At temperatures greater than 250.degree. C., the semi-insulating gallium arsenide substrate begins to conduct significant amounts of current. The highly resistive AlAs buffer layer limits this increased conduction, thus permitting device operation at temperatures where parasitic leakage currents would impede or prevent device operation. Devices fabricated with AlAs buffer layers exhibited lower drain parasitic leakage currents and showed improved output conductance characteristics at 350.degree. C. ambient temperature.

Abstract: The incorporation of an aluminum arsenide (AlAs) buffer layer in a gallium arsenide (GaAs) field effect transistor (FET) structure is found to improve the overall device performance, particularly in the high temperature operating regime. Similar characteristics may be obtained from devices fabricated with an Al.sub.x Ga.sub.1-x As (0.2.ltoreq.x.ltoreq.1) barrier layer. At temperatures greater than 250.degree. C., the semi-insulating gallium arsenide substrate begins to conduct significant amounts of current. The highly resistive AlAs buffer layer limits this increased conduction, thus permitting device operation at temperatures where parasitic leakage currents would impede or prevent device operation. Devices fabricated with AlAs buffer layers exhibited lower drain parasitic leakage currents and showed improved output conductance characteristics at 350.degree. C. ambient temperature.