Abstract: A first node to cause flushing data units stored in a write buffer of a second node to a memory of the second node. While using a pin-based approach, the central processing unit (CPU) of the first node may activate a first pin coupled to a second pin of the second node that may cause a sequence of operations to flush the write buffer. While using a control-register based approach, the CPU or the memory controller hub (MCH) may configure the control register using an inter-node path such as the SMBus or a data transfer path that may cause a sequence of operations to flush the write buffer. While using an in-band flush mechanism, the CPU may send a message over the data transfer path after transferring the data units that may cause a sequence of operations to flush the write buffer.

Abstract: An apparatus for enabling EEPROM functionality using a flash memory device comprises a number of bytes of non-volatile memory. The flash memory device has per-byte source isolation and per-byte drain isolation of a number of non-volatile flash memory cell transistors. The flash memory device provides a byte-alterable non-volatile memory.