Patents by Inventor Chris J. Walter

Chris J. Walter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7795864
    Abstract: A casing inspection device with magnets and a multi-component flux sensors. The multicomponent sensor enables better definition of the size of defects, particularly in the azimuthal direction.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: September 14, 2010
    Assignee: Baker Hughes Incorporated
    Inventors: Joseph Gregory Barolak, Douglas W. Spencer, Jerry E. Miller, Bruce I. Girrell, Jason A. Lynch, Chris J. Walter
  • Patent number: 7595636
    Abstract: A casing inspection device with magnets and flux sensors. Measurements of axial motion of the device are used to get better definition of the axial extent of casing defects. A contact device may be used for motion measurement. The output of the contact device may be used to control the acquisition of flux measurements direction.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: September 29, 2009
    Assignee: Baker Hughes Incorporated
    Inventors: Joseph Gregory Barolak, Douglas W. Spencer, Jerry E. Miller, Bruce I. Girrell, Jason A. Lynch, Chris J. Walter
  • Patent number: 7403000
    Abstract: A casing inspection device with magnets and flux sensors. The sensors provide measurements of absolute levels of magnetic flux that are indicative of changes in casing thickness and/or permeability.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: July 22, 2008
    Assignee: Baker Hughes Incorporated
    Inventors: Joseph Gregory Barolak, Douglas W. Spencer, Jerry E. Miller, Bruce I. Girrell, Jason A. Lynch, Chris J. Walter
  • Patent number: 5392291
    Abstract: A communication method and apparatus incorporating fault-tolerance and increased transmission reliability in a content-induced transaction overlap (CITO) system is disclosed. The system is driven by an error-detecting and correcting CITO-based protocol whereby transient failures are transparent to the user. A parity check is built into the protocol for detecting failures due to hard faults. A redundancy configuration is also disclosed which permits circumvention of fabrication defects, thereby allowing an increased manufacturing yield.
    Type: Grant
    Filed: May 20, 1991
    Date of Patent: February 21, 1995
    Assignee: AlliedSignal Inc.
    Inventors: Semyon Berkovich, Chris J. Walter, Henry C. Yee
  • Patent number: 5295257
    Abstract: A method for synchronizing a distributed multiple clock system in which the first clock to reach a first predetermined number of counts generates a polling request signal. The remaining clocks compare the content of their counters to determine if they are in synchronization with the clock that generated the polling request signal. Each clock will place itself inactive if it determines it is out of synchronization with the active clocks. The first active clock to reach a second predetermined number of counts will generate a synchronization interrupt signal which resets a counter in each clock to zero. A start subroutine readmits inactive clocks when after a synchronization interrupt signal is generated its counts are within a predetermined readmittance range or its counter counts up to a third predetermined value.
    Type: Grant
    Filed: May 24, 1991
    Date of Patent: March 15, 1994
    Assignee: AlliedSignal Inc.
    Inventors: Simon Y. Berkovich, Steven A. Haaser, Henry C. Yee, Chris J. Walter
  • Patent number: 4980857
    Abstract: A task communicator for each node in a multiple node processing system having a data memory storing data received from a voter interface which is used for the execution of tasks by an associated applications processor, a next task register storing the identification code of the next task to be executed by the applications processor received from a scheduler through a scheduler interface. An input handler passes the identification code of the next task and the data required for the execution of that task to an input FIFO register interfacing the applications processor. An output FIFO register temporarily stores the data generated by the applications processor and an output handler generates inter-node messages containing data stored in the output FIFO and passes these inter-node messages to a transmitter through a transmitter interface for transmission to all of the other nodes in the processing system.
    Type: Grant
    Filed: June 7, 1989
    Date of Patent: December 25, 1990
    Assignee: Allied-Signal Inc.
    Inventors: Chris J. Walter, Roger M. Kieckhafer, Alan M. Finn
  • Patent number: 4972415
    Abstract: A voter subsystem for a multiple node fault tolerant system having an upper medial value sorter for sorting a plurality of received values to generate an upper medial value and a lower medial value sorter for sorting the same plurality of received values to generate a lower medial value. An averaging circuit adds the upper and lower medial values then divides by two to generate a voted value. A deviance checker checks each of the plurality of received values against the voted value to generate a deviance error for each received value which differed from the voted value by a predetermied amount. A loader loads the plurality of received values into the upper and lower medial value sorters and the deviance checker bit-by-bit, starting from the most significant bit positions through the least significant bit positions. The upper and lower medial value sorters and deviance checker process the received values on-the-fly in the order they are received.
    Type: Grant
    Filed: June 7, 1989
    Date of Patent: November 20, 1990
    Assignee: Allied-Signal Inc.
    Inventors: Chris J. Walter, Roger M. Kieckhafer, Alan M. Finn
  • Patent number: 4933940
    Abstract: A fault tolerator for an operations controller of a multiple node fault tolerant processing system having a data memory for storing the content of all received error free messages, an error file for storing the content of all received inner node error reports, an error handler for generating a base penalty count for each node based on the content of the errors recorded in the error file and for excluding each node from the operation of the multiple node processing system whose base penalty count exceeds an exclusion threshold. The fault tolerator also includes a synchronizer interface for passing the selected fields of the received messages to a synchronizer, a scheduler interface for passing selected information to a scheduler, and a message interface which stores the error free messages in the data memory and passes the selected fields of the messages to the synchronizer.
    Type: Grant
    Filed: May 12, 1989
    Date of Patent: June 12, 1990
    Assignee: Allied-Signal Inc.
    Inventors: Chris J. Walter, Roger M. Kiekhafer, Alan M. Finn
  • Patent number: 4914657
    Abstract: An operations controller for a multiple node fault tolerant processing system having a transmitter for transmitting inter-node messages, a plurality of receivers, each receiving inter-node messages from only one of the nodes and a message checker for checking each received message for physical and logical errors. A fault tolerator assembles all of the errors detected and decides which nodes are faulty based on the number and severity of the detected errors. A voter generates a voted value for each value which is received from the other nodes which is stored in a data memory by a task communicator. A scheduler selects the tasks to be executed by an applications processor which is passed to the task communicator. The task communicator passes the selected task and the data required for the execution of that task to the applications processor and transmits the data resulting from that task to all of the nodes in the system.
    Type: Grant
    Filed: April 15, 1987
    Date of Patent: April 3, 1990
    Assignee: Allied-Signal Inc.
    Inventors: Chris J. Walter, Roger M. Kieckhafer, Alan M. Finn
  • Patent number: 4868814
    Abstract: A method and apparatus is described for distributing data in a hierarchically connected system (10) comprising a plurality of nodes (12-25) at each of a plurality of hierarchical levels, one or more bidirectional buses (29-30, 31,32) interconnecting mutually exclusive nodes at each hierarchical level, and a sender (49) for receiving and transmitting data located at each node (12-25) for transmitting and receiving data under the Content Induced Transaction Overlap (CITO) protocol and for transmitting and receiving data without regard to the CITO protocol. Each bidirectional bus (27-32) is interconnected through a node to a node on a bidirectional bus at a higher hierarchical level. Several virtual buses may be formed for distribution of the messages over one or more bidirectional buses (27-33) by controlling the senders (90,92,94,96) at each node by a slot controller (88) which activates the senders (90,92,94,96) as a function of time slot.
    Type: Grant
    Filed: July 22, 1988
    Date of Patent: September 19, 1989
    Assignee: Allied-Signal Inc.
    Inventors: Semyon Berkovich, Henry C. Yee, Chris J. Walter
  • Patent number: 4816989
    Abstract: A synchronizer for each node in a multiple node processing system having a message interface for receiving sync and pre-sync time-dependent message, counter means for generating a local time, a time stamp memory having an entry for each node in the multiple node processing system, a time stamper responsive to receiving a time-dependent message from a node for storing the local time in the entry of said time stamp memory for that node to generate a time stamp.
    Type: Grant
    Filed: April 15, 1987
    Date of Patent: March 28, 1989
    Assignee: Allied-Signal Inc.
    Inventors: Alan M. Finn, Roger M. Kieckhafer, Chris J. Walter
  • Patent number: 4805107
    Abstract: A task scheduler for a fault tolerant multiple node processing system having a task activity list storing a set of application tasks, a priority scan list storing a selected portion of the set of application tasks, a completion status list also storing the same selected portion of the set of application tasks. A wake-up sequencer transfers the application tasks from the task activity list to the priority scan list, and a priority scanner transfers the application tasks ready for execution from the priority scan list to a selection queue. A next task selector selects the next application task that its node will execute, and a task started register stores the identity of the application tasks completed by the other nodes. A task interactive consistency (TIC) handler updates the status of the application tasks stored in the task activity list, the priority scan list, and the completion status list in response to messages received from the other nodes identifying which nodes completed tasks.
    Type: Grant
    Filed: April 15, 1987
    Date of Patent: February 14, 1989
    Assignee: Allied-Signal Inc.
    Inventors: Roger M. Kieckhafer, Alan M. Finn, Chris J. Walter
  • Patent number: 4598411
    Abstract: An on-the-fly data compression system for compressing the data transmitted between a data source and an ultimate utilization device. The system normally has two data compression modules implementing a conventional multi-buffering scheme and a decoder for reconstructing the compressed data to its original format. The data compression modules compresses the data using a word representation by associative processing buffer and a content induced transaction overlap transmission protocol which results in an interleaved transmission of data bits and bit position bits, the latter being indicative of the number of data bits that will be transmitted during the subsequent data transmission. The decoder reconstructs the compressed data to its original format in response to the transmitted data and bit position bits and stores them in a pair of buffers in the sequential order in which they were generated.
    Type: Grant
    Filed: July 17, 1984
    Date of Patent: July 1, 1986
    Assignee: Allied Corporation
    Inventors: Semyon Berkovich, Colleen R. Wilson, Chris J. Walter
  • Patent number: 4493074
    Abstract: A content induced transaction overlap communication system for transmitting data over a single communication channel between a plurality of senders and at least one receiver. The senders simultaneously transmit the highest order bits of their data word, one bit at a time in serial fashion and monitor the state of the communication channel. Transmission of data bits is terminated by all senders which detect a difference between the state of their transmitted data bit and the state of the communication channel. Bit competition performed at the end of each transmitted data word determines among those senders still having data bits remaining to be transmitted which sender has lexicographically the next smallest word and activates that sender to transmit its remaining data bits. This procedure continues until all of the senders have completed the sending of their data word.
    Type: Grant
    Filed: November 3, 1982
    Date of Patent: January 8, 1985
    Assignee: The Bendix Corporation
    Inventors: Chris J. Walter, Colleen R. Wilson, Semyon Berkovich
  • Patent number: 4484192
    Abstract: Disclosed is a moving map display having a mass memory storing a complete map of the terrain to be traversed by a vehicle, a scan memory storing a portion of the complete map corresponding to the area immediately surrounding the vehicle, a computer for controlling the updating of the portion of map stored in the scan memory and for controlling the refreshing of the map data displayed on a cathode ray tube display, a scan memory address generator receiving parameters computed by the computer for generating addresses sequential outputting the digital map data stored in the scan memory in a predetermined sequence, a video display generator for converting the map data output from the scan memory for utilization by the cathode ray tube display, and a timing generator for synchronizing the generation of the addresses by the scan memory address generator with the scan field of the cathode ray tube display.
    Type: Grant
    Filed: December 17, 1981
    Date of Patent: November 20, 1984
    Assignee: The Bendix Corporation
    Inventors: William R. Seitz, Harry R. Farrah, Gerald A. Brumm, Lansing B. Evans, Chris J. Walter
  • Patent number: 4477802
    Abstract: An address generator responsible to input parameters for generating addresses to read out the content of a memory along parallel lines disposed at an angle to the orthogonal rows and columns of storage elements. The address generator has a first pair of registers coupled by an adder to generate line corrected X addresses, a second pair of registers coupled by an adder for generating first address corrections, an adder summing said line corrected X addresses with said first address corrections to generate X addresses, a third pair of registers coupled by an adder to generate line corrected Y addresses, a fourth pair of registers coupled by an adder to generate second address corrections, and an adder summing said line corrected Y addresses with said second address corrections to generate Y addresses.
    Type: Grant
    Filed: December 17, 1981
    Date of Patent: October 16, 1984
    Assignee: The Bendix Corporation
    Inventors: Chris J. Walter, Gerald A. Brumm