Abstract: A process methodology and application for change control monitoring and identification used with a circuit board testing platform. This methodology uses “baselines” to track an approved collection of changes for testing a circuit board. An approver is an authorized user or a user that have permission to modify board-test parameters. Modifications of board-test parameters made by unauthorized persons are reported though a change notification system that can alert quality control systems so corrective action of the change can be taken. The change notification system associates the identity of the circuit board to the changes being made. The system uses digital signature encryption to protect the integrity and verifiability of the data from the test system and prevents data forgery.

Abstract: A method and apparatus is presented for gaining socket testability through the use of a capacitive interposer engineered to create capacitive coupling between signal nodes of a circuit assembly that the tester has access to and nodes of the socket that would not otherwise have any coupling to a testable signal node of the socket. Generally, coupling capacitance is engineered into the interposer by trace and via routing between the signal node of the socket and a location in close proximity to the inaccessible socket node such that their proximity to each other couples them together.

Abstract: An in-circuit test fixture performs both electrical tests on a Printed Circuit Assembly (“PCA”) and reads distinguishing features of a feature of interest of the PCA. The in-circuit test fixture physically supports an image sensor array. A light focusing means has a position relative to the distinguishing features and the image sensor such that a focused real image of the distinguishing features is imaged onto the image sensor. The image sensor outputs image information of the distinguishing features. A processor performs image analysis based on the image information of the distinguishing features to determine if defects exist.

Abstract: A method and apparatus for detecting open defects on grounded nodes of an electrical device using capacitive lead frame technology is presented. In accordance with the method of the invention, an accessible signal node that is capacitively coupled the grounded node is stimulated with a known source signal. A capacitive sense plate is capacitively coupled to the stimulated node and grounded node of the electrical device, and a measuring device coupled to the capacitive sense plate capacitively senses a resulting signal. The value of the capacitively sensed signal is indicative of the presence or non-presence of an open defect on one or both of the grounded node and stimulated signal node.

Abstract: A device for enabling testing of electrical paths through a circuit assembly is presented. The device may include a non-contact connector test probe for a testing a connector of the circuit assembly. A method for testing continuity of electrical paths through a circuit assembly is presented. In the method, one or more nodes of the circuit assembly are stimulated, connector pins of a connector on the circuit assembly are capacitively coupled to a non-contact connector test probe, and an electrical characteristic is measured by a tester coupled to the non-contact connector test probe to determine continuity of electrical paths through the circuit assembly.

Abstract: A twisting fixture probe for cleaning oxides, residues or other contaminants from the surface of a solder bead probe and probing a solder bead probe on a printed circuit board during in-circuit testing.

Abstract: A method for testing for a defect condition on a node-under-implicit-test of an electrical device is presented. The technique according to the invention includes stimulating a first node of the electrical device that is capacitively coupled to the node-under-implicit-test with a known source signal, and capacitively sensing a signal on a second node of the electrical device that is capacitively coupled to the node-under-implicit-test. A defect condition such as a short or open can be determined from the capacitively sensed signal.

Abstract: Techniques for automating probing location selection during printed circuit board (PCB) and corresponding PCB tester fixture design are presented. The invention includes a system and algorithm for selecting a probe layout comprising a set of probing locations for a printed circuit board design having a plurality of nets, at least some of which have a number of alternative possible probing locations. The system and algorithm iteratively generates a potential probe layout comprising one or more probing locations per net, and based on the potential probe layout, determines one or more regions of maximum deflection. A probing location from the potential probe layout that is located in a region of maximum deflection and is associated with a net having one or more alternative probing locations is removed from the potential probe layout and replaced in the with one of the one or more alternate probing locations associated with the net.

Abstract: Techniques for automating test pad insertion in a printed circuit board (PCB) design and fixture probes insertion in a PCB tester fixture are presented. A probe location algorithm predictably determines respective preferred probing locations from among respective sets of potential probing locations associated with a number of respective nets in a PCB design. Test pads, preferably in the form of bead probes, are added to the PCB design at the respective preferred probing locations along with, where feasible, one or more alternate probing locations chosen from among remaining ones of the respective sets of potential probing locations. During fixture design, nets with multiple test pads implemented in the PCB design are processed by the same probe location algorithm used during PCB design to determine the associated preferred probing location and any associated alternate probing locations for said respective nets.

Abstract: Techniques for automating test pad insertion in a printed circuit board (PCB) design and fixture probe insertion in a PCB tester fixture are presented. A probe location algorithm predictably determines respective preferred probing locations from among respective sets of potential probing locations associated with a number of respective nets in a PCB design. Test pads, preferably in the form of bead probes, are added to the PCB design at the respective preferred probing locations along with, where feasible, one or more alternate probing locations chosen from among remaining ones of the respective sets of potential probing locations. During fixture design, nets with multiple test pads implemented in the PCB design are processed by the same probe location algorithm used during PCB design to determine the associated preferred and alternate probing locations for said respective nets.

Abstract: A twisting fixture probe for cleaning oxides, residues or other contaminants from the surface of a solder bead probe and probing a solder bead probe on a printed circuit board during in-circuit testing.

Abstract: A test access point structure for accessing test points of a printed circuit board and method of fabrication thereof is presented. Each test access point structure is conductively connected to a trace at a test access point and above an exposed surface of the printed circuit board to be accessible for probing by a fixture probe. The test access point structure may be designed and manufactured to permit deformation of the test access point structure upon initial probing of the test access point structure with a fixture probe to ensure electrical contact between the fixture probe and the test access point structure.

Abstract: A device for enabling testing of electrical paths through a circuit assembly is presented. The device may include a non-contact connector test probe for a testing a connector of the circuit assembly. A method for testing continuity of electrical paths through a circuit assembly is presented. In the method, one or more nodes of the circuit assembly are stimulated, connector pins of a connector on the circuit assembly are capacitively coupled to a non-contact connector test probe, and an electrical characteristic is measured by a tester coupled to the non-contact connector test probe to determine continuity of electrical paths through the circuit assembly.

Abstract: Methods for forming X-ray images having 0.25 .mu.m minimum line widths on X-ray sensitive material are presented. A holgraphic image of a desired circuit pattern is projected onto a wafer or other image-receiving substrate to allow recording of the desired image in photoresist material. In one embodiment, the method uses on-axis transmission and provides a high flux X-ray source having modest monochromaticity and coherence requirements. A layer of light-sensitive photoresist material on a wafer with a selected surface is provided to receive the image(s). The hologram has variable optical thickness and variable associated optical phase angle and amplitude attenuation for transmission of the X-rays. A second embodiment uses off-axis holography. The wafer receives the holographic image by grazing incidence reflection from a hologram printed on a flat metal or other highly reflecting surface or substrate.

Abstract: A non-contact X-ray projection lithography method for producing a desired X-ray image on a selected surface of an X-ray-sensitive material, such as photoresist material on a wafer, the desired X-ray image having image minimum linewidths as small as 0.063 .mu.m, or even smaller. A hologram and its position are determined that will produce the desired image on the selected surface when the hologram is irradiated with X-rays from a suitably monochromatic X-ray source of a selected wavelength .lambda.. On-axis X-ray transmission through, or off-axis X-ray reflection from, a hologram may be used here, with very different requirements for monochromaticity, flux and brightness of the X-ray source. For reasonable penetration of photoresist materials by X-rays produced by the X-ray source, the wavelength X, is preferably chosen to be no more than 13.5 nm in one embodiment and more preferably is chosen in the range 1-5 nm in the other embodiment.