Patents by Inventor Chris K. Ridgway

Chris K. Ridgway has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mitigating single-event upsets using containerization
    Patent number: 11367499
    Abstract: A computing system is disclosed. The computing system includes a computation unit, one or more processors, a volatile memory, and a non-volatile memory communicatively coupled to the one or more processors and having instructions stored thereon, which when executed by the one or more processors, causing the one or more processor to instantiate a container and perform at least one of a volatile memory checking procedure or a non-volatile memory checking procedure. The volatile memory checking procedure includes checking the first physical address space for errors, loading a container into volatile memory containing the first physical address space if an error is determined, rechecking the first physical address space for error, loading the container to a second physical address space and updating a memory management unit if an error in the first physical address space is determined.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: June 21, 2022
    Assignee: Rockwell Collins, Inc.
    Inventors: John V. Thommana, Chris K. Ridgway, Joseph Kaemmer
  • MITIGATING SINGLE-EVENT UPSETS USING CONTAINERIZATION
    Publication number: 20220068421
    Abstract: A computing system is disclosed. The computing system includes a computation unit, one or more processors, a volatile memory, and a non-volatile memory communicatively coupled to the one or more processors and having instructions stored thereon, which when executed by the one or more processors, causing the one or more processor to instantiate a container and perform at least one of a volatile memory checking procedure or a non-volatile memory checking procedure. The volatile memory checking procedure includes checking the first physical address space for errors, loading a container into volatile memory containing the first physical address space if an error is determined, rechecking the first physical address space for error, loading the container to a second physical address space and updating a memory management unit if an error in the first physical address space is determined.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Inventors: John V. Thommana, Chris K. Ridgway, Joseph Kaemmer