Abstract: An engine comprises one or more cylinders, each cylinder comprising a piston, a connecting rod, a crank shaft, and a crankpin, wherein the crankpin further comprises a main crankpin and a crankpin extension, wherein the connecting rod is affixed at one end to the piston and at another end to a first end of the crankpin extension, wherein a second end of the crankpin extension is affixed to a first end of the main crankpin, and wherein a second end of the main crankpin is affixed to the crankshaft.

Abstract: An engine comprises one or more cylinders, each cylinder comprising a piston, a connecting rod, a crank shaft, and a crankpin, wherein the crankpin further comprises a main crankpin and a crankpin extension, wherein the connecting rod is affixed at one end to the piston and at another end to a first end of the crankpin extension, wherein a second end of the crankpin extension is affixed to a first end of the main crankpin, and wherein a second end of the main crankpin is affixed to the crankshaft.

Abstract: An engine comprises one or more cylinders, each cylinder comprising a piston, a connecting rod, a crank shaft, and a crankpin, wherein the crankpin further comprises a main crankpin and a crankpin extension, wherein the connecting rod is affixed at one end to the piston and at another end to a first end of the crankpin extension, wherein a second end of the crankpin extension is affixed to a first end of the main crankpin, and wherein a second end of the main crankpin is affixed to the crankshaft.

Abstract: An engine comprises one or more cylinders, each cylinder comprising a piston, a connecting rod, a crank shaft, and a crankpin, wherein the crankpin further comprises a main crankpin and a crankpin extension, wherein the connecting rod is affixed at one end to the piston and at another end to a first end of the crankpin extension, wherein a second end of the crankpin extension is affixed to a first end of the main crankpin, and wherein a second end of the main crankpin is affixed to the crankshaft, so that when the piston is at top dead center of the power stroke, the torque at the crankshaft is substantially greater than zero.

Abstract: A digital apparatus for phase aligning output signals of a silicon device to an applied input clock signal in same device allows synchronization of data transfers between the device and another device such as a controller. It includes a digital or analog oscillator of higher frequencies than the applied clock and in multiples of powers 2n where n=1, 2, 4, etc., with provisions for synchronization and control by the applied input clock. The main oscillator frequency is subdivided to lower frequencies. An internally derived duplicate frequency clock is phase shifted by either 45 or 22.5 degrees. The system measure both a desired coarse delay, and a fine delay to be applied to the path to phase align the output signal to the phase of the applied input clock.

Abstract: A Flash memory system includes N flash devices, where N is an integer, each flash device having a flash device interface consisting of a control signal line, a R/B signal line, and a I/O signal line, and wherein each flash device has an operating speed of s. A logic block is connected to each flash device interface, and is further connected to a controller which whose interfaces also has a control signal line, a R/B signal line, and a I/O signal line, so that controller operates at an operating speed of N times s, and wherein the logic block controls each flash device simultaneously.

Abstract: A system for converting the energy created by the ignition of fuel in one or more cylinders of an internal combustion engine to rotational power, having a piston within each of its cylinders, includes one or more first connecting rods, each rotatingly affixed at a first end to the corresponding piston, a master crank to which each such first connecting rod is rotatingly attached at a second, a load crank and one or more second connecting rods, the number corresponding to the number of first connecting rods, each second connecting rod rotatingly affixed at one end to the master crank, and at the other end to the load crank. The second connecting rods may be of the same length as that of the first connecting rods, or of different length.

Abstract: An Active edge connector for memory modules has a base including two PCB sides and a spacer separating the sides, with driver chips mounted on each side of each side, printed wiring electrically connecting a first set of electrical signals from each of the driver chips to a mother board on which the connector is mounted, and printed wiring for electrically connecting a second set of electrical signals from each of the driver chips to a memory module inserted in the edge connector. When a group of connectors are mounted on a mother board, electrical signals arriving at the first connector are routed to its driver chips, producing re-driven signals to the next connector, and so on. A decoder circuit provides addressing signals determining the last such connector to which the signals are intended, and which prevents the signals from going to any connectors containing memories not addressed.

Abstract: A packaging technology for silicon chips is similar to ball grid array packaging technology of the prior art without, however, the use of printed board substrate of the prior art Instead pins are used that are part of a planar frame, the pins folded to a position 90 degrees from the plane of the frame, after which the frame is disposed in contact with the chip, pads on the frame and the chip are connected, and then entire assembly is then encapsulated. The edges of the frame are then cut off, leaving the encapsulation to maintain the configuration of the package in place.

Abstract: A digital apparatus for phase aligning output signals of a silicon device to an applied input clock signal in same device allows synchronization of data transfers between the device and another device such as a controller. It includes a digital or analog oscillator of higher frequencies than the applied clock and in multiples of powers 2n where n=1, 2, 4, etc., with provisions for synchronization and control by the applied input clock. The main oscillator frequency is subdivided to lower frequencies. An internally derived duplicate frequency clock is phase shifted by either 45 or 22.5 degrees. The system measure both a desired coarse delay, and a fine delay to be applied to the path to phase align the output signal to the phase of the applied input clock.

Abstract: A Flash memory system includes N flash devices, where N is an integer, each flash device having a flash device interface consisting of a control signal line, a R/B signal line, and a I/O signal line, and wherein each flash device has an operating speed of s. A logic block is connected to each flash device interface, and is further connected to a controller which whose interfaces also has a control signal line, a R/B signal line, and a I/O signal line, so that controller operates at an operating speed of N times s, and wherein the logic block controls each flash device simultaneously.

Abstract: A packaging technology for silicon chips is similar to ball grid array packaging technology of the prior art without, however, the use of printed board substrate of the prior art Instead pins are used that are part of a planar frame, the pins folded to a position 90 degrees from the plane of the frame, after which the frame is disposed in contact with the chip, pads on the frame and the chip are connected, and then entire assembly is then encapsulated. The edges of the frame are then cut off, leaving the encapsulation to maintain the configuration of the package in place.

Abstract: An Active edge connector for memory modules has a base including two PCB sides and a spacer separating the sides, with driver chips mounted on each side of each side, printed wiring electrically connecting a first set of electrical signals from each of the driver chips to a mother board on which the connector is mounted, and printed wiring for electrically connecting a second set of electrical signals from each of the driver chips to a memory module inserted in the edge connector. When a group of connectors are mounted on a mother board, electrical signals arriving at the first connector are routed to its driver chips, producing re-driven signals to the next connector, and so on. A decoder circuit provides addressing signals determining the last such connector to which the signals are intended, and which prevents the signals from going to any connectors containing memories not addressed.

Abstract: A system for converting the energy created by the ignition of fuel in one or more cylinders of an internal combustion engine to rotational power, having a piston within each of its cylinders, includes one or more first connecting rods, each rotatingly affixed at a first end to the corresponding piston, a master crank to which each such first connecting rod is rotatingly attached at a second, a load crank and one or more second connecting rods, the number corresponding to the number of first connecting rods, each second connecting rod rotatingly affixed at one end to the master crank, and at the other end to the load crank. The second connecting rods may be of the same length as that of the first connecting rods, or of different length.

Abstract: A Flash memory system includes N flash devices, where N is an integer, each flash device having a flash device interface consisting of a control signal line, a R/B signal line, and a I/O signal line, and wherein each flash device has an operating speed of s. A logic block is connected to each flash device interface, and is further connected to a controller which whose interfaces also has a control signal line, a R/B signal line, and a I/O signal line, so that controller operates at an operating speed of N times s, and wherein the logic block controls each flash device simultaneously.

Abstract: A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal f1 is the input to both the ring oscillator and the High-Frequency Digital Oscillator, which has a multiplicity of output signals including f2, f4, and f8 at one-half, one fourth, and one-eighth the frequency of fn respectively, and wherein an input gating signal causes the oscillator to start or stop, a signal fc=¼*(f4) causing a coarse frequency adjustment and a signal ?=(1/f1?1/fc) making a fine adjustment, and by stopping the new output before the rising edge of f1; and then restarting starting the new output at the rising edge of so that the output and input are synchronized.

Abstract: A packaging technology for silicon chips is similar to ball grid array packaging technology of the prior art without, however, the use of printed board substrate of the prior art Instead pins are used that are part of a planar frame, the pins folded to a position 90 degrees from the plane of the frame, after which the frame is disposed in contact with the chip, pads on the frame and the chip are connected, and then entire assembly is then encapsulated. The edges of the frame are then cut off, leaving the encapsulation to maintain the configuration of the package in place.

Abstract: A method for synchronizing an output signal of a device phase aligned with an input clock includes the steps of providing an oscillator signal having a period ?n of 1/(f1*2n), wherein f1 is the clock frequency, and wherein the oscillator signal is phase aligned with the input clock signal, so a multiple of the clock frequency is produced. A number of delayed signals are generated, each having the same period as the input clock signal, but delayed by multiples of one-half the oscillator period from the input clock. The phase difference between the unadjusted output signal each delayed signal is determined, and the smallest value of the phase difference calculated. This smallest phase difference value is then added to the clock signal, resulting in a delayed clock, which is then used to generated the delayed output signal, which will be in close synchronization with the input clock.

Abstract: An Active edge connector for memory modules has a base including two PCB sides and a spacer separating the sides, with driver chips mounted on each side of each side, printed wiring electrically connecting a first set of electrical signals from each of the driver chips to a mother board on which the connector is mounted, and printed wiring for electrically connecting a second set of electrical signals from each of the driver chips to a memory module inserted in the edge connector. When a group of connectors are mounted on a mother board, electrical signals arriving at the first connector are routed to its driver chips, producing re-driven signals to the next connector, and so on. A decoder circuit provides addressing signals determining the last such connector to which the signals are intended, and which prevents the signals from going to any connectors containing memories not addressed.

Abstract: A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal f1 is the input to both the ring oscillator and the High-Frequency Digital Oscillator, which has a multiplicity of output signals including f2, f4, and f8 at one-half, one fourth, and one-eighth the frequency of fn respectively, and wherein an input gating signal causes the oscillator to start or stop, a signal fc=¼*(f4) causing a coarse frequency adjustment and a signal ?=(1/f1?1/fc) making a fine adjustment, and by stopping the new output before the rising edge of f1; and then restarting starting the new output at the rising edge of so that the output and input are synchronized.