Patents by Inventor Chris Lane
Chris Lane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240366885Abstract: Medication delivery methods, devices and systems are provided. The medication delivery device includes a retractable sheath mechanism connected to a distal end of the device. The retractable sheath mechanism is axially movable between a first position to cover a needle attached to the distal end and a second position to expose the needle with an adjustable protrusion length. The retractable sheath mechanism includes one or more skin sensors disposed on an end surface thereof to detect skin before and during injection. In some cases, a needle carousel is provided to connect to the distal end of the device. The needle carousel supports multiple needle capsules each including a needle.Type: ApplicationFiled: May 3, 2024Publication date: November 7, 2024Inventors: Rachael Price, Matthew Clemente, Laurie Mendelson, Apurva Jadhav, Horst Pitchler, Amy Connell, Matthew Johnson, Namisha Lnu, Christina Bode, Ian Hanson, Aaron Morgan, Jane Zhang, Jenny Nguyen, Pawel Drozdz, Sarah Vaughan, Scott Telstad, Olga Smelyanets, Jorge A. Balderrama Canales, Janet Wu Chenie Chastain, Thomas Dean Jordan, Corydon A. Hinton, John Fresquez, David Lane, Chris Puryear, Peter Kimball, Vidya Saptharishi, Paul Pasika, Ashwin Sriram
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Patent number: 12122005Abstract: An improved tooling, including: a base housing having an interior and tooling holes, the tooling holes being configured to receive alignment studs attached to a tooling fixture; a first clamping fixture and a second clamping fixture fit inside hollowed regions within the base housing; a shaft having a length and an axis along the length of the shaft, the shaft situated inside the base housing and the shaft having a first threaded region and a second threaded region to connect the first clamping fixture and the second clamping fixture, whereby rotation of the shaft causes the first clamping fixture and the second clamping fixture to move towards and away from each other along the axis of the shaft; each of the first clamping fixture and the second clamping fixture comprising one or more securing mechanisms configured to: engage and disengage the alignment studs based upon rotation of the shaft.Type: GrantFiled: July 14, 2022Date of Patent: October 22, 2024Assignee: 5th Axis Inc.Inventors: Chris Taylor, Steve Grangetto, Adam Lane
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Patent number: 10669553Abstract: This invention disclosure relates to novel maize starch. The starch can be made from the newly developed waxy sugary-2 double-mutant maize that has low activity of Granule Bound Starch Synthase I (GBSSI), which results in low amylose level. The starch from newly developed waxy sugary-2 double-mutant is freeze-thaw stable and has high viscosity. In comparison with the starch of the existing waxy sugary-2 double-mutant maize, the new waxy sugary-2 double-mutant maize starch showed, inter alia, improved pasting profile, starch granule integrity, larger starch granule size, and higher viscosity.Type: GrantFiled: April 26, 2018Date of Patent: June 2, 2020Assignee: Corn Products Development, Inc.Inventors: Hongxin Jiang, Brad Ostrander, Chris Lane
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Publication number: 20180327767Abstract: This invention disclosure relates to novel maize starch. The starch can be made from the newly developed waxy sugary-2 double-mutant maize that has low activity of Granule Bound Starch Synthase I (GBSSI), which results in low amylose level. The starch from newly developed waxy sugary-2 double-mutant is freeze-thaw stable and has high viscosity. In comparison with the starch of the existing waxy sugary-2 double-mutant maize, the new waxy sugary-2 double-mutant maize starch showed, inter alia, improved pasting profile, starch granule integrity, larger starch granule size, and higher viscosity.Type: ApplicationFiled: April 26, 2018Publication date: November 15, 2018Inventors: Hongxin Jiang, Brad Ostrander, Chris Lane
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Patent number: 9988641Abstract: This invention disclosure relates to novel maize starch. The starch can be made from the newly developed waxy sugary-2 double-mutant maize that has low activity of Granule Bound Starch Synthase I (GBSSI), which results in low amylose level. The starch from newly developed waxy sugary-2 double-mutant is freeze-thaw stable and has high viscosity. In comparison with the starch of the existing waxy sugary-2 double-mutant maize, the new waxy sugary-2 double-mutant maize starch showed, inter alia, improved pasting profile, starch granule integrity, larger starch granule size, and higher viscosity.Type: GrantFiled: April 21, 2016Date of Patent: June 5, 2018Assignee: Corn Products Development, Inc.Inventors: Hongxin Jiang, Brad Ostrander, Chris Lane
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Publication number: 20170283818Abstract: This invention disclosure relates to novel maize starch. The starch can be made from the newly developed waxy sugary-2 double-mutant maize that has low activity of Granule Bound Starch Synthase I (GBSSI), which results in low amylose level. The starch from newly developed waxy sugary-2 double-mutant is freeze-thaw stable and has high viscosity. In comparison with the starch of the existing waxy sugary-2 double-mutant maize, the new waxy sugary-2 double-mutant maize starch showed, inter alia, improved pasting profile, starch granule integrity, larger starch granule size, and higher viscosity.Type: ApplicationFiled: April 21, 2016Publication date: October 5, 2017Inventors: Hongxin JIANG, Brad Ostrander, Chris Lane
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Patent number: 8201129Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: GrantFiled: May 13, 2009Date of Patent: June 12, 2012Assignee: Altera CorporationInventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
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Patent number: 8191025Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.Type: GrantFiled: September 1, 2009Date of Patent: May 29, 2012Assignee: Altera CorporationInventors: Michael Chan, Paul Leventis, David Lewis, Ketan Zaveri, Hyun Mo Yi, Chris Lane
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Patent number: 7644386Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.Type: GrantFiled: January 17, 2007Date of Patent: January 5, 2010Assignee: Altera CorporationInventors: Michael Chan, Paul Leventis, David Lewis, Ketan Zaveri, Hyun Mo Yi, Chris Lane
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Publication number: 20090224800Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: ApplicationFiled: May 13, 2009Publication date: September 10, 2009Applicant: ALTERA CORPORATIONInventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
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Patent number: 7584447Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: GrantFiled: August 12, 2005Date of Patent: September 1, 2009Assignee: Altera CorporationInventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
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Patent number: 7512849Abstract: A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.Type: GrantFiled: December 5, 2005Date of Patent: March 31, 2009Assignee: Altera CorporationInventors: Tim Allen, Michael Fairman, Mario Guzman, Bryan Hoyer, Chris Lane, Kerry Veenstra, Keith Duwel, Andy L. Lee
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Publication number: 20080129588Abstract: A method and apparatus for determining a location of a mobile station (“MS”) in a Global-Navigation-Satellite System is disclosed. The method includes obtaining an estimate of position associated with a mobile-country code (“MCC-position estimate”), wherein the mobile-country code is associated with a given country, and wherein the MCC-position estimate comprises an measure of uncertainty. The method also includes using the MCC-position estimate as a position of the mobile station (“MS position”) when the measure of uncertainty satisfies a given threshold. The MCC-position estimate may include, for example, a centroid of population (“population centroid”); the population centroid and a uncertainty measure associated with the population centroid; a centroid of geography (“geographic centroid”), the geographic centroid and an uncertainty measure associated with the geographic centroid, and/or any combination thereof.Type: ApplicationFiled: January 15, 2008Publication date: June 5, 2008Inventors: David Albert Lundgren, Chris Lane, Steven Malkos
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Patent number: 7253660Abstract: A multiplexing device is described. In one embodiment, the multiplexing device includes: a hardwired multiplexer including a plurality of input terminals; a plurality of select terminals; and at least one output terminal, where the plurality of input terminals are coupled to a plurality of block input lines or a plurality of functional element input terminals. In one embodiment, the plurality of input terminals are hardwired to the plurality of block input lines or the plurality of functional element input terminals. In one embodiment, the plurality of select terminals are coupled to a second plurality of functional element input terminals or a plurality of functional element output terminals. In one embodiment, the plurality of block input lines include a plurality of logic array block (LAB) lines, the plurality of functional element input terminals include a plurality of logic element (LE) input terminals, and the plurality of functional element output terminals include LE output terminals.Type: GrantFiled: November 27, 2002Date of Patent: August 7, 2007Assignee: Altera CorporationInventors: Paul Leventis, Bruce Pedersen, Chris Lane, Srinivas Reddy, David Lewis
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Patent number: 7180324Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.Type: GrantFiled: May 28, 2004Date of Patent: February 20, 2007Assignee: Altera CorporationInventors: Michael Chan, Paul Leventis, David Lewis, Ketan Zaveri, Hyun Mo Yi, Chris Lane
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Patent number: 7112992Abstract: An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset of programmable functions may be reprogrammed by loading configuration data into the first plurality of configuration elements such that the subset of programmable functions may be reprogrammed without necessarily reprogramming other programmable functions of the electronic device.Type: GrantFiled: December 8, 2004Date of Patent: September 26, 2006Assignee: Altera CorporationInventors: Mario Guzman, Chris Lane, Andy L. Lee, Ninh Ngo
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Patent number: 7058920Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: GrantFiled: June 11, 2003Date of Patent: June 6, 2006Assignee: Altera CorporationInventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
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Publication number: 20060033527Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: ApplicationFiled: August 12, 2005Publication date: February 16, 2006Inventors: Andy Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Betz, David Lewis
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Patent number: 7000161Abstract: A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.Type: GrantFiled: October 11, 2002Date of Patent: February 14, 2006Assignee: Altera CorporationInventors: Tim Allen, Michael Fairman, Mario Guzman, Bryan Hoyer, Chris Lane, Kerry Veenstra, Keith Duwel, Andy L. Lee
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Publication number: 20050264318Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.Type: ApplicationFiled: May 28, 2004Publication date: December 1, 2005Applicant: Altera CorporationInventors: Michael Chan, Paul Leventis, David Lewis, Ketan Zaveri, Hyun Yi, Chris Lane