Patents by Inventor Chris Lane

Chris Lane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11915826
    Abstract: An example device is configured to capture an image of a patient. The devices includes a camera configured to capture the image of the patient. The device further: captures contextual data associated with the image; allows a caregiver to select the image to be stored; forwards the image and the contextual data to a remote server for processing using artificial intelligence; and receives a proposed diagnosis from the remote server based upon the image and the contextual data.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: February 27, 2024
    Assignee: Welch Allyn, Inc.
    Inventors: John A. Lane, Chris R. Roberts, Thomas A. Gurgol, WonKyung McSweeney
  • Patent number: 10669553
    Abstract: This invention disclosure relates to novel maize starch. The starch can be made from the newly developed waxy sugary-2 double-mutant maize that has low activity of Granule Bound Starch Synthase I (GBSSI), which results in low amylose level. The starch from newly developed waxy sugary-2 double-mutant is freeze-thaw stable and has high viscosity. In comparison with the starch of the existing waxy sugary-2 double-mutant maize, the new waxy sugary-2 double-mutant maize starch showed, inter alia, improved pasting profile, starch granule integrity, larger starch granule size, and higher viscosity.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: June 2, 2020
    Assignee: Corn Products Development, Inc.
    Inventors: Hongxin Jiang, Brad Ostrander, Chris Lane
  • Publication number: 20180327767
    Abstract: This invention disclosure relates to novel maize starch. The starch can be made from the newly developed waxy sugary-2 double-mutant maize that has low activity of Granule Bound Starch Synthase I (GBSSI), which results in low amylose level. The starch from newly developed waxy sugary-2 double-mutant is freeze-thaw stable and has high viscosity. In comparison with the starch of the existing waxy sugary-2 double-mutant maize, the new waxy sugary-2 double-mutant maize starch showed, inter alia, improved pasting profile, starch granule integrity, larger starch granule size, and higher viscosity.
    Type: Application
    Filed: April 26, 2018
    Publication date: November 15, 2018
    Inventors: Hongxin Jiang, Brad Ostrander, Chris Lane
  • Patent number: 9988641
    Abstract: This invention disclosure relates to novel maize starch. The starch can be made from the newly developed waxy sugary-2 double-mutant maize that has low activity of Granule Bound Starch Synthase I (GBSSI), which results in low amylose level. The starch from newly developed waxy sugary-2 double-mutant is freeze-thaw stable and has high viscosity. In comparison with the starch of the existing waxy sugary-2 double-mutant maize, the new waxy sugary-2 double-mutant maize starch showed, inter alia, improved pasting profile, starch granule integrity, larger starch granule size, and higher viscosity.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: June 5, 2018
    Assignee: Corn Products Development, Inc.
    Inventors: Hongxin Jiang, Brad Ostrander, Chris Lane
  • Publication number: 20170283818
    Abstract: This invention disclosure relates to novel maize starch. The starch can be made from the newly developed waxy sugary-2 double-mutant maize that has low activity of Granule Bound Starch Synthase I (GBSSI), which results in low amylose level. The starch from newly developed waxy sugary-2 double-mutant is freeze-thaw stable and has high viscosity. In comparison with the starch of the existing waxy sugary-2 double-mutant maize, the new waxy sugary-2 double-mutant maize starch showed, inter alia, improved pasting profile, starch granule integrity, larger starch granule size, and higher viscosity.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 5, 2017
    Inventors: Hongxin JIANG, Brad Ostrander, Chris Lane
  • Patent number: 8201129
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: June 12, 2012
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
  • Patent number: 8191025
    Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: May 29, 2012
    Assignee: Altera Corporation
    Inventors: Michael Chan, Paul Leventis, David Lewis, Ketan Zaveri, Hyun Mo Yi, Chris Lane
  • Patent number: 7644386
    Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: January 5, 2010
    Assignee: Altera Corporation
    Inventors: Michael Chan, Paul Leventis, David Lewis, Ketan Zaveri, Hyun Mo Yi, Chris Lane
  • Publication number: 20090224800
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Application
    Filed: May 13, 2009
    Publication date: September 10, 2009
    Applicant: ALTERA CORPORATION
    Inventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
  • Patent number: 7584447
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: September 1, 2009
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
  • Patent number: 7512849
    Abstract: A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: March 31, 2009
    Assignee: Altera Corporation
    Inventors: Tim Allen, Michael Fairman, Mario Guzman, Bryan Hoyer, Chris Lane, Kerry Veenstra, Keith Duwel, Andy L. Lee
  • Publication number: 20080129588
    Abstract: A method and apparatus for determining a location of a mobile station (“MS”) in a Global-Navigation-Satellite System is disclosed. The method includes obtaining an estimate of position associated with a mobile-country code (“MCC-position estimate”), wherein the mobile-country code is associated with a given country, and wherein the MCC-position estimate comprises an measure of uncertainty. The method also includes using the MCC-position estimate as a position of the mobile station (“MS position”) when the measure of uncertainty satisfies a given threshold. The MCC-position estimate may include, for example, a centroid of population (“population centroid”); the population centroid and a uncertainty measure associated with the population centroid; a centroid of geography (“geographic centroid”), the geographic centroid and an uncertainty measure associated with the geographic centroid, and/or any combination thereof.
    Type: Application
    Filed: January 15, 2008
    Publication date: June 5, 2008
    Inventors: David Albert Lundgren, Chris Lane, Steven Malkos
  • Patent number: 7253660
    Abstract: A multiplexing device is described. In one embodiment, the multiplexing device includes: a hardwired multiplexer including a plurality of input terminals; a plurality of select terminals; and at least one output terminal, where the plurality of input terminals are coupled to a plurality of block input lines or a plurality of functional element input terminals. In one embodiment, the plurality of input terminals are hardwired to the plurality of block input lines or the plurality of functional element input terminals. In one embodiment, the plurality of select terminals are coupled to a second plurality of functional element input terminals or a plurality of functional element output terminals. In one embodiment, the plurality of block input lines include a plurality of logic array block (LAB) lines, the plurality of functional element input terminals include a plurality of logic element (LE) input terminals, and the plurality of functional element output terminals include LE output terminals.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: August 7, 2007
    Assignee: Altera Corporation
    Inventors: Paul Leventis, Bruce Pedersen, Chris Lane, Srinivas Reddy, David Lewis
  • Patent number: 7180324
    Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: February 20, 2007
    Assignee: Altera Corporation
    Inventors: Michael Chan, Paul Leventis, David Lewis, Ketan Zaveri, Hyun Mo Yi, Chris Lane
  • Patent number: 7112992
    Abstract: An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset of programmable functions may be reprogrammed by loading configuration data into the first plurality of configuration elements such that the subset of programmable functions may be reprogrammed without necessarily reprogramming other programmable functions of the electronic device.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: September 26, 2006
    Assignee: Altera Corporation
    Inventors: Mario Guzman, Chris Lane, Andy L. Lee, Ninh Ngo
  • Patent number: 7058920
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: June 6, 2006
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
  • Publication number: 20060033527
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Application
    Filed: August 12, 2005
    Publication date: February 16, 2006
    Inventors: Andy Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Betz, David Lewis
  • Patent number: 7000161
    Abstract: A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: February 14, 2006
    Assignee: Altera Corporation
    Inventors: Tim Allen, Michael Fairman, Mario Guzman, Bryan Hoyer, Chris Lane, Kerry Veenstra, Keith Duwel, Andy L. Lee
  • Publication number: 20050264318
    Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 1, 2005
    Applicant: Altera Corporation
    Inventors: Michael Chan, Paul Leventis, David Lewis, Ketan Zaveri, Hyun Yi, Chris Lane
  • Publication number: 20030237071
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Application
    Filed: June 11, 2003
    Publication date: December 25, 2003
    Inventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis