Patents by Inventor Chris Larsen
Chris Larsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11095666Abstract: The disclosed computer-implemented method for detecting covert channels structured in Internet Protocol (IP) transactions may include (1) intercepting an IP transaction including textual data and a corresponding address, (2) evaluating the textual data against a model to determine a difference score, (3) determining that the textual data is suspicious when the difference score exceeds a threshold value associated with the model, (4) examining, upon determining that the textual data is suspicious, the address in the transaction to determine whether the address is invalid, (5) analyzing the transaction to determine a frequency of address requests that have been initiated from a source address over a predetermined period, and (6) identifying the transaction as a covert data channel for initiating a malware attack when the address is determined to be invalid and the frequency of the address requests exceeds a threshold value. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: August 28, 2018Date of Patent: August 17, 2021Assignee: CA, INC.Inventors: Qing Li, Chris Larsen, Jon DiMaggio
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Patent number: 10060078Abstract: The present disclosure generally relates to a railroad chassis vehicle having independently operable workheads for carrying out rail maintenance operations on non-uniform sections of railroad tracks. Related methods of operation of the railroad chassis and associated maintenance of ballast beds underlying railroad tracks are also described.Type: GrantFiled: September 26, 2016Date of Patent: August 28, 2018Assignee: HARSCO TECHNOLOGIES LLCInventors: Victor Vargas, Chris Larsen
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Patent number: 9679964Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.Type: GrantFiled: September 14, 2015Date of Patent: June 13, 2017Assignee: Micron Technologies, Inc.Inventors: Chris Larsen, Alex J. Schrinsky, John D. Hopkins, Matthew J. King
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Publication number: 20170096779Abstract: The present disclosure generally relates to a railroad chassis vehicle having independently operable workheads for carrying out rail maintenance operations on non-uniform sections of railroad tracks. Related methods of operation of the railroad chassis and associated maintenance of ballast beds underlying railroad tracks are also described.Type: ApplicationFiled: September 26, 2016Publication date: April 6, 2017Inventors: Victor Vargas, Chris Larsen
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Publication number: 20160005815Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.Type: ApplicationFiled: September 14, 2015Publication date: January 7, 2016Applicant: Micron Technology, Inc.Inventors: Chris Larsen, Alex J. Schrinsky, John D. Hopkins, Matthew J. King
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Patent number: 9136331Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.Type: GrantFiled: April 10, 2013Date of Patent: September 15, 2015Assignee: Micron Technology, Inc.Inventors: Chris Larsen, Alex J. Schrinsky, John D. Hopkins, Matthew King
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Publication number: 20140306323Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.Type: ApplicationFiled: April 10, 2013Publication date: October 16, 2014Applicant: Micron Technology, Inc.Inventors: Chris Larsen, Alex J. Schrinsky, John D. Hopkins, Matthew King
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Patent number: 8729621Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: GrantFiled: October 8, 2013Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventors: Kirk D. Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Publication number: 20140035021Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: ApplicationFiled: October 8, 2013Publication date: February 6, 2014Applicant: Micron Technology, Inc.Inventors: Kirk D. Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Patent number: 8580645Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: GrantFiled: March 6, 2013Date of Patent: November 12, 2013Assignee: Micron Technology, Inc.Inventors: Kirk D. Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Patent number: 8450789Abstract: Memory arrays and their formation are disclosed. One such memory array has first and second memory cells over a semiconductor, an air gap between the first and second memory cells, and an isolation region within the semiconductor and under the air gap so that the isolation region is aligned with the air gap.Type: GrantFiled: August 24, 2010Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Andrew Bicksler, Chris Larsen
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Patent number: 8415223Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: GrantFiled: February 3, 2012Date of Patent: April 9, 2013Assignee: Micron Technology, Inc.Inventors: Kirk D. Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Publication number: 20120132979Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: ApplicationFiled: February 3, 2012Publication date: May 31, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Patent number: 8129781Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: GrantFiled: September 28, 2010Date of Patent: March 6, 2012Assignee: Micron Technology, Inc.Inventors: Kirk D Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Publication number: 20120049245Abstract: Memory arrays and their formation are disclosed. One such memory array has first and second memory cells over a semiconductor, an air gap between the first and second memory cells, and an isolation region within the semiconductor and under the air gap so that the isolation region is aligned with the air gap.Type: ApplicationFiled: August 24, 2010Publication date: March 1, 2012Inventors: Andrew Bicksler, Chris Larsen
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Publication number: 20110013463Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: ApplicationFiled: September 28, 2010Publication date: January 20, 2011Applicant: Micron Technology, Inc.Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Patent number: 7824994Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: GrantFiled: November 14, 2008Date of Patent: November 2, 2010Assignee: Micron Technology, Inc.Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Publication number: 20090068812Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: ApplicationFiled: November 14, 2008Publication date: March 12, 2009Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Patent number: 7485528Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: GrantFiled: July 14, 2006Date of Patent: February 3, 2009Assignee: Micron Technology, Inc.Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Publication number: 20080014698Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: ApplicationFiled: July 14, 2006Publication date: January 17, 2008Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen