Patents by Inventor Chris Macnamara

Chris Macnamara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11451470
    Abstract: A Service Routing Agent and methods are disclosed that classify and route data service requests. One embodiment includes a control circuit and at least one orchestrator, processor, and service handler circuit. The control circuit performs a process to: receive a configuration of at least one service handler circuit, initialize a list of service handler circuits and associated applications, program the at least one processor to listen for data service requests associated with the application, receive a data service request, and determine whether a service handler circuit associated with the application has been activated; when the service handler circuit has been activated, forwards the data service request to the service handler circuit, and when the service handler circuit has not been activated, request that the service handler circuit be activated, and then forwards the data service request to the service handler circuit. The Service Routing Agent reports updated traffic statistics.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: September 20, 2022
    Assignee: INTEL CORPORATION
    Inventors: Damien Power, Chris MacNamara, Marco Varlese
  • Patent number: 11431565
    Abstract: Examples include techniques for monitoring a data packet transfer rate at an interface queue, and based at least in part on a comparison of the data packet transfer rate to a threshold, assigning the interface queue from a core of a first class to a core of a second class or assigning the interface queue from a core of the second class to a core of the first class.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Mohammad Abdul Awal, Jasvinder Singh, Reshma Pattan, David Hunt, Declan Doherty, Chris Macnamara
  • Patent number: 11418495
    Abstract: Techniques and apparatuses for processing data unit are described. In one embodiment, for example, an apparatus for networking may include at least one memory, logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to access an encrypted packet having an encrypted portion, determine at least one flow control segment of the encrypted portion, decrypt the at least one flow control segment to generate a partially-decrypted packet comprising a decrypted at least one flow control segment and an encrypted remainder portion, the remainder portion comprising a portion of the encrypted packet that does not include the decrypted at least one flow control segment, access process information in the decrypted at least one flow control segment, and process the partially-decrypted packet according to the process information. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: August 16, 2022
    Inventors: John J. Browne, Chris Macnamara, Namakkal N. Venkatesan, Tomasz Kantecki, Declan W. Doherty
  • Patent number: 11388074
    Abstract: Technologies for performance monitoring include a computing device having multiple processor cores. The computing device performs a training workload with a processor core by continuously polling an empty input queue. The computing device determines empty polling thresholds based on the empty polling workload. The computing device performs a packet processing workload with one or more processor cores by continuously polling input queues associated with network traffic. The computing device compares a measured number of empty polls performed by the packet processing workload against the empty polling thresholds. The computing device configures power management of one or more processor cores in response to the comparison. The computing device may determine empty polling trends and compare the measured number of empty polls and the empty polling trends to the empty polling thresholds. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Peter McCarthy, Chris MacNamara, John Browne, Liang J. Ma, Liam Day
  • Publication number: 20220155847
    Abstract: Examples described herein relate to circuitry to cause a processor to enter reduced power consumption state and circuitry to, based on a write to one or more of multiple memory regions, cause the processor to exit reduced power consumption state, wherein the multiple memory regions store receive descriptors associated with one or more packets received by a network interface device. In some examples, multiple memory regions are defined by a driver of the network interface device. In some examples, the reduced power consumption state comprises a TPAUSE state.
    Type: Application
    Filed: December 22, 2021
    Publication date: May 19, 2022
    Inventors: Konstantin ANANYEV, Anatoly BURAKOV, David HUNT, Chris MACNAMARA, Edwin VERPLANKE, Omkar MASLEKAR, Gilbert NEIGER, Rajesh M. SANKARAN
  • Publication number: 20220129031
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Application
    Filed: November 5, 2021
    Publication date: April 28, 2022
    Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
  • Patent number: 11190450
    Abstract: This disclosure is directed to system to monitor and control data flow in a network. At least one device in a core network may be responsible for charging functions related to the data requests. During certain high usage scenarios (e.g., emergencies, special events, etc.), it may be possible for the charging system to be overwhelmed. For example, a policing system may be implemented in the core network to at least manage the flow of requests to the charging system. The policing system may monitor and control request flow to the charging system based on at least one policy. When a request is determined to violate a policy, the policing system may take corrective action to prevent the charging system from being overwhelmed. For example, the policing system may block the request, divert the request to another charging system that may have available capacity, etc.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Damien Power, Chris Macnamara, Sinead Murtagh, Laura Hunt, Gary Loughnane
  • Patent number: 11169560
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris Macnamara, John J. Browne, Ripan Das
  • Publication number: 20210320870
    Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventors: Patrick CONNOR, Andrey CHILIKIN, Brendan RYAN, Chris MACNAMARA, John J. BROWNE, Krishnamurthy JAMBUR SATHYANARAYANA, Stephen DOYLE, Tomasz KANTECKI, Anthony KELLY, Ciara LOFTUS, Fiona TRAHE
  • Patent number: 11144085
    Abstract: An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Asma H. Al-Rawi, Federico Ardanaz, Jonathan M. Eastep, Dorit Shapira, Krishnakanth Sistla, Nikhil Gupta, Vasudevan Srinivasan, Chris MacNamara
  • Patent number: 11115283
    Abstract: Methods, systems, and computer programs are presented for managing resources to deliver a network service in a distributed configuration. A method includes an operation for identifying resources for delivering a network service, the resources being classified by geographic area. Further, the method includes operations for selecting service agents to configure the identified resources, each service agent to manage service pools for delivering the network service across at least one geographic area, the service agents being selected to provide configurability for the service pools. The method further includes operations for sending configuration rules, to the service agents, configured to establish service pools for delivering the network service across the geographic areas. Service traffic information is collected from the service agents, and the resources are adjusted based on the collected service traffic information.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Damien Power, Alan Carey, Chris MacNamara
  • Patent number: 11070476
    Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Patrick Connor, Andrey Chilikin, Brendan Ryan, Chris MacNamara, John J. Browne, Krishnamurthy Jambur Sathyanarayana, Stephen Doyle, Tomasz Kantecki, Anthony Kelly, Ciara Loftus, Fiona Trahe
  • Patent number: 11038819
    Abstract: Technologies for distributing network packet workload are disclosed. A compute device may receive a network packet and determine network packet extrinsic entropy information that is based on information that is not part of the contents of the network packet, such as an arrival time of the network packet. The compute device may use the extrinsic entropy information to assign the network packet to one of several packet processing queues. Since the assignment of network packets to the packet processing queues depend at least in part on extrinsic entropy information, similar or even identical packets will not necessarily be assigned to the same packet processing queue.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Ronen Chayat, Andrey Chilikin, Chris Macnamara, Maryam Tahhan, Giovanni Cabiddu
  • Publication number: 20210157626
    Abstract: Examples described herein relate to circuitry to boot a virtualized execution environment (VEE) by use of system resources, wherein the system resources are allocated based on a priority level of the VEE. In some examples, the circuitry to boot a VEE by use of system resources is to access an identification of system resources to use to boot the VEE and priority level of the VEE from stored data. In some examples, the priority level of the VEE is based on a service level agreement (SLA), service level objective (SLO), or class of service (COS) that identifies boot time of the VEE. In some examples, the circuitry is to boot a VEE by use of system resources, wherein the system resources are allocated based on a priority level of the VEE and also based on a number of VEEs that boot concurrently.
    Type: Application
    Filed: February 2, 2021
    Publication date: May 27, 2021
    Inventors: Amruta MISRA, Chris MACNAMARA, John J. BROWNE, Liang MA, Shobhi JAIN, David HUNT
  • Patent number: 10999209
    Abstract: Technologies for network packet processing include a computing device that receives incoming network packets. The computing device adds the incoming network packets to an input lockless shared ring, and then classifies the network packets. After classification, the computing device adds the network packets to multiple lockless shared traffic class rings, with each ring associated with a traffic class and output port. The computing device may allocate bandwidth between network packets active during a scheduling quantum in the traffic class rings associated with an output port, schedule the network packets in the traffic class rings for transmission, and then transmit the network packets in response to scheduling. The computing device may perform traffic class separation in parallel with bandwidth allocation and traffic scheduling. In some embodiments, the computing device may perform bandwidth allocation and/or traffic scheduling on each traffic class ring in parallel.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: John J. Browne, Tomasz Kantecki, Chris Macnamara, Pierre Laurent, Sean Harte, Peter McCarthy, Jacqueline F. Jardim, Liang Ma
  • Patent number: 10966135
    Abstract: Aspects of data re-direction are described, which can include software-defined networking (SDN) data re-direction operations. Some aspects include data re-direction operations performed by one or more virtualized network functions. In some aspects, a network router decodes an indication of a handover of a user equipment (UE) from a first end point (EP) to a second EP, based on the indication, the router can update a relocation table including the UE identifier, an identifier of the first EP, and an identifier of the second EP. The router can receive a data packet for the UE, configured for transmission to the first EP, and modify the data packet, based on the relocation table, for rerouting to the second EP. In some aspects, the router can decode handover prediction information, including an indication of a predicted future geographic location of the UE, and update the relocation table based on the handover prediction information.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Jonas Svennebring, Niall D. McDonnell, Andrey Chilikin, Andrew Cunningham, Chris MacNamara, Carl-Oscar Montelius, Eliezer Tamir, Bjorn Topel
  • Patent number: 10936449
    Abstract: Discussed herein are component redundancy systems, devices, and methods. A method to transfer a workload from a first component to a second component of a same device may include monitoring a wear indicator associated with the first component, and in response to an indication that the first component is stressed based on the wear indicator, transferring a workload of the first component to the second component.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Hang T. Nguyen, Stephen T. Palermo, John J. Browne, Chris MacNamara, Pradeepsunder Ganesh
  • Publication number: 20210049285
    Abstract: Examples described herein relate to a manner of provide a time of life of data. In some examples, data and control parameters are received from a data source. The data can be encrypted and stored. In addition, at least a portion of the control parameters can be stored into a distributed ledger. In some examples, the portion of the control parameters include an indicator of expiration time of the data. In some examples, a data header for the data is generated, where the data header includes an indication that the data is subject to a limited life span and a data identifier. The data header can be accessed with a request to access the encrypted data. In some examples, a request to determine if the data is valid and accessible is provided to a node of the distributed ledger and an indication of whether the data is valid and accessible is received from a node in the distributed ledger.
    Type: Application
    Filed: October 28, 2020
    Publication date: February 18, 2021
    Inventors: Sundar VEDANTHAM, Bin LIN, Pravin PATHAK, Ximing CHEN, Chris MACNAMARA
  • Publication number: 20210014324
    Abstract: Examples described herein relate to a network interface apparatus that includes an interface; circuitry to determine whether to store content of a received packet into a cache or into a memory, at least during a configuration of the network interface to store content directly into the cache, based at least in part on a fill level of a region of the cache allocated to receive copies of packet content directly from the network interface; and circuitry to store content of the received packet into the cache or the memory based on the determination, wherein the cache is external to the network interface. In some examples, the network interface is to determine to store content of the received packet into the memory based at least in part on a fill level of the region of the cache being identified as full or determine to store content of the received packet into the cache based at least in part on a fill level of the region of the cache being identified as not filled.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 14, 2021
    Inventors: Andrey CHILIKIN, Tomasz KANTECKI, Chris MACNAMARA, John J. BROWNE, Declan DOHERTY, Niall POWER
  • Publication number: 20200409755
    Abstract: Methods to automatically prioritize input/output (I/O) for Network Function Virtualization (NFV) workloads at platform overload and associated apparatus and mechanisms. During lab or runtime workload operations, various platform telemetry data are collected and analyzed to determine whether a current workload is uncore-sensitive—that is, sensitive to operations involving utilization of the uncore circuitry such as I/O-related operations, memory bandwidth utilization, LLC utilization, network traffic, core-to-core traffic etc. For uncore sensitive workloads, upon detection of a platform overload condition such as a thermal load approaching a TDP limit, the uncore circuitry is prioritized over the core circuitry such that the frequency of the core is reduced first. A closed-loop feedback mechanism is used to adjust the frequencies of the core and uncore under various workload conditions. The mechanism enables I/O throughput to be maintained for NFV workloads, while reducing the processor thermal load.
    Type: Application
    Filed: September 16, 2020
    Publication date: December 31, 2020
    Inventors: Chris MacNamara, Amruta Misra, John Browne