Patents by Inventor Chris Macnamara

Chris Macnamara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240143505
    Abstract: Methods and apparatus for dynamic selection of super queue size for CPUs with higher number of cores. An apparatus includes a plurality of compute modules, each module including a plurality of processor cores with integrated first level (L1) caches and a shared second level (L2) cache, a plurality of Last Level Caches (LLCs) or LLC blocks and a plurality of memory interface blocks interconnect via a mesh interconnect. A compute module is configured to arbitrate access to the shared L2 cache and enqueue L2 cache misses in a super queue (XQ). The compute module further is configured to dynamically adjust the size of the XQ during runtime operations. The compute module tracks parameters comprising an L2 miss rate or count and LLC hit latency and adjusts the XQ size as a function of these parameters. A lookup table using the L2 miss rate/count and LLC hit latency may be implemented to dynamically select the XQ size.
    Type: Application
    Filed: December 22, 2023
    Publication date: May 2, 2024
    Inventors: Amruta MISRA, Ajay RAMJI, Rajendrakumar CHINNAIYAN, Chris MACNAMARA, Karan PUTTANNAIAH, Pushpendra KUMAR, Vrinda KHIRWADKAR, Sanjeevkumar Shankrappa ROKHADE, John J. BROWNE, Francesc GUIM BERNAT, Karthik KUMAR, Farheena Tazeen SYEDA
  • Publication number: 20240089206
    Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Patrick CONNOR, Andrey CHILIKIN, Brendan RYAN, Chris MACNAMARA, John J. BROWNE, Krishnamurthy JAMBUR SATHYANARAYANA, Stephen DOYLE, Tomasz KANTECKI, Anthony KELLY, Ciara LOFTUS, Fiona TRAHE
  • Publication number: 20240012459
    Abstract: Examples described herein relate to receiving a configuration, wherein the configuration is to specify a first level of renewable energy utilized by one or more devices based on telemetry, wherein the telemetry comprises a level of renewable energy supplied to the one or more devices. Based on a second level of available supplied renewable energy, a portion of the first level of available supplied renewable energy can be allocated to one or more devices to perform the process. Based on a third level of available supplied renewable energy, increase renewable energy allocated to the one or more devices, to perform the process, to above the first level.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Applicant: Intel Corporation
    Inventors: Francesc GUIM BERNAT, Karthik KUMAR, John J. BROWNE, Chris MACNAMARA, Patrick CONNOR
  • Patent number: 11855897
    Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Patrick Connor, Andrey Chilikin, Brendan Ryan, Chris MacNamara, John J. Browne, Krishnamurthy Jambur Sathyanarayana, Stephen Doyle, Tomasz Kantecki, Anthony Kelly, Ciara Loftus, Fiona Trahe
  • Publication number: 20230412459
    Abstract: Technologies for dynamically selecting resources for virtual switching include a computing device configured to identify a present demand on processing resources of the computing device that are configured to process data associated with network packets received by the computing device. Additionally, the computing device is configured to determine a present capacity of one or more acceleration resources of the computing device and configure the virtual switch based on the present demand and the present capacity of the acceleration resources. Other embodiments are described herein.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Inventors: Ciara Loftus, Chris MacNamara, John J. Browne, Patrick Fleming, Tomasz Kantecki, John BARRY, Patrick Connor
  • Patent number: 11847008
    Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 19, 2023
    Assignee: Intel Corporation
    Inventors: David Hunt, Niall Power, Kevin Devey, Changzheng Wei, Bruce Richardson, Eliezer Tamir, Andrew Cunningham, Chris MacNamara, Nemanja Marjanovic, Rory Sexton, John Browne
  • Publication number: 20230353508
    Abstract: Examples described herein relate to a system within a package. In some examples, the system includes a communication fabric and circuitry to adjust a packet throughput rate associated with the communication fabric based at least in part on incoming receive rate across multiple input ports and fabric usage. In some examples, the communication fabric is to communicatively couple devices in the package including one or more of: an accelerator, a processor, a memory, or a network interface device.
    Type: Application
    Filed: July 10, 2023
    Publication date: November 2, 2023
    Inventors: Kapil SOOD, Patrick CONNOR, Scott P. DUBAL, James R. HEARN, Brendan RYAN, Chris MACNAMARA, Conor WALSH, David HUNT, John J. BROWNE, Kevin LAATZ
  • Patent number: 11805065
    Abstract: Packets are differentiated based on their traffic class. A traffic class is allocated bandwidth for transmission. One or more core or thread can be allocated to process packets of a traffic class for transmission based on allocated bandwidth for that traffic class. If multiple traffic classes are allocated bandwidth, and a traffic class underutilizes allocated bandwidth or a traffic class is allocated insufficient bandwidth, then allocated bandwidth can be adjusted for a future transmission time slot. For example, a higher priority traffic class with excess bandwidth can share the excess bandwidth with a next highest priority traffic class for use to allocate packets for transmission for the same time slot.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 31, 2023
    Assignee: Intel Corporation
    Inventors: Jasvinder Singh, John J. Browne, Tomasz Kantecki, Chris Macnamara
  • Publication number: 20230315143
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
  • Patent number: 11703906
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
  • Patent number: 11703933
    Abstract: Examples described herein provide for a first core to map a measurement of packet processing activity and operating parameters so that a second core can access the measurement of packet processing activity and potentially modify an operating parameter of the first core. The second core can modify operating parameters of the first core based on the measurement of packet processing activity. The first and second cores can be provisioned on start-up with a common key. The first and second cores can use the common key to encrypt or decrypt measurement of packet processing activity and operating parameters that are shared between the first and second cores. Accordingly, operating parameters of the first core can be modified by a different core while providing for secure modification of operating parameters.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Liang Ma, Weigang Li, Madhusudana Raghupatruni, Hongjun Ni, Xuekun Hu, Changzheng Wei, Chris MacNamara, John J. Browne
  • Patent number: 11671382
    Abstract: Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: June 6, 2023
    Assignee: Intel Corporation
    Inventors: John J. Browne, Seán Harte, Tomasz Kantecki, Pierre Laurent, Chris MacNamara
  • Patent number: 11665062
    Abstract: Methods, systems, and computer programs are presented for managing resources to deliver a network service in a distributed configuration. A method includes an operation for identifying resources for delivering a network service, the resources being classified by geographic area. Further, the method includes operations for selecting service agents to configure the identified resources, each service agent to manage service pools for delivering the network service across at least one geographic area, the service agents being selected to provide configurability for the service pools. The method further includes operations for sending configuration rules, to the service agents, configured to establish service pools for delivering the network service across the geographic areas. Service traffic information is collected from the service agents, and the resources are adjusted based on the collected service traffic information.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: May 30, 2023
    Assignee: Intel Corporation
    Inventors: Damien Power, Alan Carey, Chris MacNamara
  • Publication number: 20230153121
    Abstract: A machine-readable storage medium having program code that when processed by one or more processing cores causes a method to be performed. The method includes determining from program code that is scheduled for execution and/or is being scheduled for execution that an accelerator is expected to be invoked by the program code. The program code to implement one or more application software processes. The method also includes, in response to the determining, causing the accelerator to wake up from a sleep state before the accelerator is first invoked from the program code's execution.
    Type: Application
    Filed: January 11, 2023
    Publication date: May 18, 2023
    Inventors: Yuzhang LUO, Haoxiang SUN, Siming WAN, Laurent COQUEREL, John J. BROWNE, Chris MACNAMARA, Fei Z. WANG
  • Patent number: 11630693
    Abstract: Technologies for power-aware scheduling include a computing device that receives network packets. The computing device classifies the network packets by priority level and then assigns each network packet to a performance group bin. The packets are assigned based on priority level and other performance criteria. The computing device schedules the network packets assigned to each performance group for processing by a processing engine such as a processor core. Network packets assigned to performance groups having a high priority level are scheduled for processing by processing engines with a high performance level. The computing device may select performance levels for processing engines based on processing workload of the network packets. The computing device may control the performance level of the processing engines, for example by controlling the frequency of processor cores. The processing workload may include packet encryption. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: April 18, 2023
    Assignee: Intel Corporation
    Inventors: John Browne, Chris MacNamara, Tomasz Kantecki, Peter McCarthy, Liang Ma, Mairtin O'Loingsigh, Rory Sexton, John Griffin, Nemanja Marjanovic, David Hunt
  • Publication number: 20230035142
    Abstract: A method is described. The method includes polling a queue a plurality of times over a plurality of intervals, where, the queue feeds work items to a processor. The method includes determining, from the polling, respective work item flow metrics for the plurality of intervals. The method includes determining a processor's performance setting based on the plurality of respective work item flow metrics.
    Type: Application
    Filed: October 14, 2022
    Publication date: February 2, 2023
    Inventors: Chris MACNAMARA, David HUNT, Kevin LAATZ, Anatoly BURAKOV, Bruce RICHARDSON, Conor WALSH, John J. BROWNE
  • Patent number: 11567556
    Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 31, 2023
    Assignee: Intel Corporation
    Inventors: Chris Macnamara, John J. Browne, Tomasz Kantecki, David Hunt, Anatoly Burakov, Srihari Makineni, Nikhil Gupta, Ankush Varma, Dorit Shapira, Vasudevan Srinivasan, Bryan T. Butters, Shrikant M. Shah
  • Publication number: 20230027516
    Abstract: A processor-to-processor agent to provide connectivity over a processor-to-processor interconnect between services/network functions on different processors on a same compute node in a server is provided. The processor-to-processor agent can intercept socket interface calls using a network traffic filter in the network stack and redirect the packets based on traffic matching rules.
    Type: Application
    Filed: September 30, 2022
    Publication date: January 26, 2023
    Inventors: Tomasz KANTECKI, Paul HOUGH, David CREMINS, Ciara LOFTUS, Aman Deep SINGH, John J. BROWNE, David HUNT, Maksim LUKOSHKOV, Amruta MISRA, Nirint SHAH, Chris MACNAMARA
  • Publication number: 20230018221
    Abstract: An apparatus can include processor cores and control circuitry coupled to the processor cores. The control circuitry can detect at least one of a power characteristic and a frequency characteristic of at least one of the processor cores. The control circuitry can determine that a frequency control opportunity is present on at least one of the processor cores based on at least one of the power characteristic and the frequency characteristic. The control circuitry can adjust a power parameter of at least one of the processor cores responsive to determining that the frequency control opportunity is present.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Inventors: Reshma Pattan, Pinkesh Shah, Chris MacNamara, Nikhil Gupta
  • Publication number: 20220393960
    Abstract: Technologies for performance monitoring include a computing device having multiple processor cores. The computing device performs a training workload with a processor core by continuously polling an empty input queue. The computing device determines empty polling thresholds based on the empty polling workload. The computing device performs a packet processing workload with one or more processor cores by continuously polling input queues associated with network traffic. The computing device compares a measured number of empty polls performed by the packet processing workload against the empty polling thresholds. The computing device configures power management of one or more processor cores in response to the comparison. The computing device may determine empty polling trends and compare the measured number of empty polls and the empty polling trends to the empty polling thresholds. Other embodiments are described and claimed.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 8, 2022
    Inventors: Peter McCarthy, Chris MacNamara, John Browne, Liang J. Ma, Liam Day