Abstract: A vending machine is disclosed. The vending machine has a selector for a plurality of beverage types and a selector for a plurality of ice types. The vending machine has a first store for storing a supply of the plurality of beverage types and a second store for storing a supply of the plurality of ice types. The vending machine also has a dispenser for dispensing into a container a selected beverage type and a selected ice type.

Abstract: Circuits, methods, and apparatus incorporate both a wireless physical interface and audio processing unit on a single integrated circuit. The wireless physical interface may include a receiver, transmitter, or a complete transceiver. The audio processing unit is typically in communication with both the wireless interface and one or more wired physical interfaces. The integrated circuit may be as simple as a wireless physical interface and audio processing unit, or it may include other circuits such as graphics processors, networking interfaces, memories, or other circuits.

Abstract: A circuit for accelerating processing of pixel data being provided to a frame buffer comprising circuitry for determining that pixel values vary linearly over a scan line of a polygon to be rendered, linear interpolation circuitry for providing pixel values using a process of linear interpolation between accurately determined pixel values, and a circuit for collecting pixel values to be written to a frame buffer until a significant number of pixel values may be written together.

Abstract: A frame buffer including a memory array, circuitry for accessing the array, a plurality of latches each capable of storing a plurality of pixel values equivalent to a large portion of a row of pixels in the array which may be read simultaneously from the array, and circuitry for writing simultaneously to the memory cells of a row of the array the data stored in the latches whereby a row of pixels may be read and written back to the array bus in a minimum time period.

Abstract: An arrangement providing frame buffer memory for an output display by which single buffer and double buffered application programs may be run singly or simultaneously is described. An array of video random access memory sufficient to store data for at least two complete frames is configured in three different ways depending on the applications being run. When only programs designed to run on a single frame buffer are run, the memory is configured as a single frame buffer. When a single program designed to run on double frame buffers is run, the memory is configured as two visible frame buffers. When multiple programs designed to run on double frame buffers are run, the memory is configured into one visible and one invisible frame buffer. Additionally, apparatus for selecting data to be furnished to the display depending on whether the program operates as a single buffered program, a double buffered program, or a plurality of double buffered programs is provided.

Abstract: A frame buffer designed to allow frame buffer operations which do not involve new row addresses to be accomplished without the need for a RAS cycle. The elimination of RAS cycles for address loading and similar functions substantially accelerates the operation of the frame buffer both as to functions which do not involve memory array addresses and those which do involve memory array addresses.

Abstract: An arrangement for assuring the compatibility of versions of software produced for a particular computer hardware architecture including a hardware version register, apparatus for providing an indication of a version of hardware being utilized to operate a particular version of software, a software version register, apparatus for providing an indication of a version of software being run on the particular version of hardware, apparatus for comparing the version of hardware and the version software, and apparatus responsive to the results of the comparison for setting defaults and enabling circuitry in the hardware so that the version of software runs correctly on the version of hardware.

Abstract: A double buffered output display system including a first frame buffer, a second frame buffer, a multiplexor for furnishing data to an output display from one of the first or the second frame buffers, apparatus for storing a signal indicating that the multiplexor is to select a different frame buffer to furnishing data to an output display, and apparatus for furnishing the stored signal to the multiplexor only at the completion of a frame on a display and before a new frame commences.

Abstract: A frame buffer for accelerating the display of graphics data on an output display device which frame buffer includes a pair of color value registers each of which may be loaded with color values prior to writing to the frame buffer. Selection means are provided for selecting pixel data from the bus, from a first of the color value registers, from the second of the color value registers, or from both color value registers simultaneously. When data is written to the frame buffer from color value registers it may be written to a number of pixel positions simultaneously.

Abstract: An apparatus for implementing, in hardware, clipping and intercoordinate comparison logic in a graphic display subsystem. Clipping is necessary when an object to be displayed is defined as being only partially contained within a pre-determined window on a video display. For example, if a rectangular window is defined in the upper left hand corner of a video display, and a line has been defined which extends from the upper left-hand corner to the lower right-hand corner of the display, the portion of the line which is outside the defined window is not displayed, i.e., it is clipped. Additionally, if a line of text is wider than the window, the portion of the line of text which is outside the window must also be clipped.

Abstract: A predictive caching system for use in computer system having at least one portion of memory in which information is stored for retrieval, a general cache used to speed the operation of accessing such memory, and a processor for controlling the access of the memory comprising apparatus for discerning a pattern of access of the memory, apparatus operating in response to the pattern determined by the apparatus for discerning a pattern of access of the memory for determining a next address which will probably accessed in such memory if the pattern discerned continues, and apparatus for storing the information at the next address determined prior to the next access of the memory whereby the information at the next address is available without the need to access the memory.

Abstract: An apparatus for implementing, in hardware, circuitry for adding a raster offset to screen coordinates in a graphics display subsystem for the purpose of displaying the image in a window which may be moved by a user to an arbitrary position on a screen display. Specifically, a pair of raster offsets, one for X coordinates and one for Y coordinates, are stored in X and Y raster offset registers. The X and Y raster offsets correspond to the offset of an active window from the origin of the screen display. These offsets are added to each coordinate which is to be displayed within the active window in a manner which does not result in any additional overhead.

Abstract: A computer graphics system comprising apparatus for drawing quadrilateral images on an output display when furnished the vertices of the quadrilateral, apparatus for providing width values for each end of a line to be displayed on an output display which width values are indirectly related to the depth of the ends of the line from the viewer, and apparatus for utilizing the width values to determine vertices of a line to be drawn by the apparatus for drawing a quadrilateral image.

Abstract: A graphics accelerator interface apparatus for receiving information to be displayed by a computer and the address of such information. Storing the addresses of vertices of a quadrilateral to be displayed by a computer, translating the addresses of vertices of a quadrilateral into signals representing the relations between each of such vertices and the others of the vertices, selectively decomposing a quadrilateral into line segment portions defining trapezoids which bound sets of scan lines, determining the coordinates of the end points of each scan line within such trapezoids, translating the coordinates of the end points into linear values for display, and storing such information for display on a computer output display.

Abstract: An apparatus and method for using a test window to improve the efficiency of clipping and inter-coordinate images which are to be displayed by a graphic display subsystem. A test window is defined which surrounds a window (the clip window) within which it is desired to render graphical images. Objects are then tested to see if their vertices are outside the test window. The utilization of this window allows for a performance optimization to be made between processing of a clipped object by a hardware based graphics subsystem which incorporates the present invention or by graphic software executed by a general purpose CPU which also interfaces to the graphics display. By properly defining the test window size relative to the clip window, objects which fall totally within the test window, will be rendered faster by the graphics subsystem rather than deferring the object to graphics software. Objects with vertices that fall outside the test window would be deferred to graphics software to render.

Abstract: Apparatus and method for using an index register which cycles modulo 4 for loading registers which contain coordinates of four vertices of quadrilateral objects, including degenerate quadrilateral objects, namely a point, a line and a triangle, which are to be displayed by a graphics display subsystem. In this manner, a software command need only define the minimum number of X,Y coordinate pairs to define the object, i.e., one coordinate pair for a point, two coordinate pairs for a line, three coordinate pairs for a triangle and two coordinate pairs for a rectangle (by defining opposite corners). Additionally, by using an index register according to the present invention, objects can be efficiently replicated.

Abstract: A method of initiating a write operation for a particular command from a first computer module through a system interface to a second computer module having data registers, and a status register which includes the steps of writing data to the data registers in the second computer module, and determining the status of the status register in the second computer module to cause the initiation of the particular command by which the reading the status of the data registers and issuing the particular command as separate steps are eliminated.

Abstract: A circuit for determining the X values of each end of a series of horizontal scan lines connecting a pair of line segments each of which is defined by a pair of vertices, the horizontal scan lines defining an area to be rendered on a computer output device, comprising first and second circuit portions, each of said circuit portions including apparatus to determine the slope of a line segment, apparatus depending on the slope for determining the beginning and ending X values for each line segment for each scan line in the area to be rendered, apparatus for causing the two circuit portions to begin operation at the same scan line, and apparatus for changing the Y value for each circuit portion to the Y value of the next adjacent scan line at the same time.

Abstract: The system of the present invention provides for the context switching of devices connected through the system's memory management unit and is particularly useful in a multi-tasking computer system in which multiple processes access the same device. In the method and apparatus of the present invention, devices that are connected to the system through the MMU are controlled using the page fault mechanism of the MMU and the page fault handler in each segment. Addresses are allocated in the process address space for each process to provide for the addressing of the devices and device queues connected through the MMU, such that one device or one device queue is mapped into one segment of each process address space that will access the device. The "valid bits" associated with each page in a segment are turned on/off by the process or operating system in order to control the device.

Abstract: In a computer graphics system in which information defining graphic images to be presented on an output display is available on a scan line basis for a pair of line segments subtending a portion of the an image to be presented. The information includes the slope of each line segment and the addresses of each line segment on each scan line. A circuit comprising two comparator subportions, each of the comparator subportions being adapted to process information regarding one edge of the portion of the image to be presented and including apparatus for receiving first signals representing values of both of the line segments to be procesed for one scan line. Comparing the signals to determine their relative X positions on the scan line, controlling the determination of the relative X positions and the slope of each line segment, and storing one of the signals compared.