Patents by Inventor Chris Michael Brueggen
Chris Michael Brueggen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210110243Abstract: Systems are methods are provided for implementing a deep learning accelerator system interface (DLASI). The DLASI connects an accelerator having a plurality of inference computation units to a memory of the host computer system during an inference operation. The DLASI allows interoperability between a main memory of a host computer, which uses 64 B cache lines, for example, and inference computation units, such as tiles, which are designed with smaller on-die memory using 16-bit words. The DLASI can include several components that function collectively to provide the interface between the server memory and a plurality of tiles. For example, the DLASI can include: a switch connected to the plurality of tiles; a host interface; a bridge connected to the switch and the host interface; and a deep learning accelerator fabric protocol. The fabric protocol can also implement a pipelining scheme which optimizes throughput of the multiple tiles of the accelerator.Type: ApplicationFiled: October 10, 2019Publication date: April 15, 2021Inventors: CRAIG WARNER, Chris Michael Brueggen, Eun Sub Lee
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Patent number: 10922178Abstract: A system includes byte-addressable non-volatile memory (NVM) modules. The system includes media controllers communicatively connected to one another over a memory semantic fabric. Each media controller is responsible for a corresponding NVM module to which the media controller is attached. The media controllers cooperatively provide redundant array of independent disks (RAID) functionality at a granularity at which the NVM modules are byte-addressable without employing a master RAID controller.Type: GrantFiled: October 31, 2018Date of Patent: February 16, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Russ W. Herrell, Chris Michael Brueggen
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Patent number: 10735030Abstract: A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.Type: GrantFiled: August 7, 2017Date of Patent: August 4, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Harvey Ray, Kevin L. Miller, Chris Michael Brueggen, Martin Foltin
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Publication number: 20200133777Abstract: A system includes byte-addressable non-volatile memory (NVM) modules. The system includes media controllers communicatively connected to one another over a memory semantic fabric. Each media controller is responsible for a corresponding NVM module to which the media controller is attached. The media controllers cooperatively provide redundant array of independent disks (RAID) functionality at a granularity at which the NVM modules are byte-addressable without employing a master RAID controller.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Inventors: Gregg B. Lesartre, Russ W. Herrell, Chris Michael Brueggen
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Patent number: 10567003Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a list decode circuit may include a syndrome calculation circuit, a symbol erasure circuit, an erasure syndrome calculation circuit and a Berlekamp-Massey algorithm circuit (BMA), and an error locator polynomial (ELP) evaluation circuit. The syndrome calculation circuit may calculate a baseline syndrome and erasure syndrome calculation circuit may calculate erasure syndromes from error locator polynomials calculated by the symbol erasure circuit. The BMA circuit may use the calculated syndromes to generate a series of ELPs, which may be used by the ELP evaluation circuit to identify error locations in a codeword.Type: GrantFiled: January 26, 2017Date of Patent: February 18, 2020Assignee: Hewlett Packard Enterprise Development LPInventor: Chris Michael Brueggen
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Patent number: 10402287Abstract: According to an example, data corruption and single point of failure is prevented in a fault-tolerant memory fabric with multiple redundancy controllers by granting, by a parity media controller, a lock of a stripe to a redundancy controller to perform a sequence on the stripe. The lock may be broken in response to determining a failure of the redundancy controller prior to completing the sequence. In response to breaking the lock, the parity cacheline of the stripe may be flagged as invalid. Also, a journal may be updated to document the breaking of the lock.Type: GrantFiled: January 30, 2015Date of Patent: September 3, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Derek Alan Sherlock, Harvey Ray, Chris Michael Brueggen
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Patent number: 10367529Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a device may include a first and second polynomial evaluation circuit, a field division circuit, a discrepancy filter, and an enhanced error locator polynomial (ELP) circuit. The first and second polynomial evaluation circuits may respectively evaluate a first and second polynomial output from a Berlekamp-Massey algorithm over a plurality of values in a finite field. The field division circuit may divide the outputs from the evaluations to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm. The discrepancy filter circuit may filter the speculative discrepancy values down to a list of potentially valid discrepancy values that may be used by the enhanced ELP circuit to generate an enhanced ELP.Type: GrantFiled: January 27, 2017Date of Patent: July 30, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Chris Michael Brueggen, Ron M. Roth
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Patent number: 10312943Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.Type: GrantFiled: March 24, 2017Date of Patent: June 4, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Craig Warner, Martin Foltin, Chris Michael Brueggen, Brian S. Birk, Harvey Ray
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Patent number: 10275307Abstract: A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.Type: GrantFiled: March 9, 2017Date of Patent: April 30, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Craig Warner, Martin Foltin, Chris Michael Brueggen
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Patent number: 10243587Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of circuits for managing results from list decode methods. In accordance with some examples disclosed herein, a plurality of potential error patterns for correcting errors in a codeword may be received. The plurality of potential error patterns may be generated using a plurality of different list decode methods. Error patterns among the plurality of potential error patterns may be determined and marked as candidate error patterns using a set of error pattern screens. Error weights may be assigned to the candidate error patterns based on a quantity of bit errors in each symbol included therein. Weights for candidate error patterns that are indicative of a memory device failure may be adjusted using a scaling factor. An error pattern among the candidate error patterns may be selected to correct the errors in the codeword based on the assigned error weights.Type: GrantFiled: February 8, 2017Date of Patent: March 26, 2019Assignee: Hewlett Packard Enterprise Developmetn LPInventors: Chris Michael Brueggen, Cesar Garzon, Jonathan George
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Publication number: 20190044546Abstract: A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.Type: ApplicationFiled: August 7, 2017Publication date: February 7, 2019Inventors: Gregg B. Lesartre, Harvey Ray, Kevin L. Miller, Chris Michael Brueggen, Martin Foltin
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Patent number: 10176043Abstract: Example implementations relate to a memory controller. For example, an apparatus includes a data storage device and a memory controller coupled to the data storage device. The memory controller is to perform, during a memory scrubbing operation, a corrective action to correct an error associated with a data block stored in the data storage device. The memory control is to determine, during the memory scrubbing operation, whether the corrective action is successful. In response to a determination that the corrective action is a failed corrective action, the memory controller is to fix a hardware failure of the data storage device based on a type of the hardware failure.Type: GrantFiled: July 1, 2014Date of Patent: January 8, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Chris Michael Brueggen, Lidia Warnes
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Publication number: 20180276068Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.Type: ApplicationFiled: March 24, 2017Publication date: September 27, 2018Inventors: Gregg B. Lesartre, Craig Warner, Martin Foltin, Chris Michael Brueggen, Brian S. Birk, Harvey Ray
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Publication number: 20180260273Abstract: A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.Type: ApplicationFiled: March 9, 2017Publication date: September 13, 2018Inventors: Gregg B. Lesartre, Craig Warner, Martin Foltin, Chris Michael Brueggen
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Patent number: 10050641Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) list manipulation circuits. In accordance with some examples disclosed herein, a list manipulation circuit may include a progressive population count circuit to generate population count values. The population count values may be fed into various types of circuits, such as list conversion circuits, list compactor circuits, and list reordering circuits.Type: GrantFiled: March 23, 2017Date of Patent: August 14, 2018Assignee: Hewlett Packard Enterprise Development LPInventor: Chris Michael Brueggen
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Publication number: 20180226994Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of circuits for managing results from list decode methods. In accordance with some examples disclosed herein, a plurality of potential error patterns for correcting errors in a codeword may be received. The plurality of potential error patterns may be generated using a plurality of different list decode methods. Error patterns among the plurality of potential error patterns may be determined and marked as candidate error patterns using a set of error pattern screens. Error weights may be assigned to the candidate error patterns based on a quantity of bit errors in each symbol included therein. Weights for candidate error patterns that are indicative of a memory device failure may be adjusted using a scaling factor. An error pattern among the candidate error patterns may be selected to correct the errors in the codeword based on the assigned error weights.Type: ApplicationFiled: February 8, 2017Publication date: August 9, 2018Inventors: Chris Michael Brueggen, Cesar Garzon, Jonathan George
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Publication number: 20180219560Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a device may include a first and second polynomial evaluation circuit, a field division circuit, a discrepancy filter, and an enhanced error locator polynomial (ELP) circuit. The first and second polynomial evaluation circuits may respectively evaluate a first and second polynomial output from a Berlekamp-Massey algorithm over a plurality of values in a finite field. The field division circuit may divide the outputs from the evaluations to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm. The discrepancy filter circuit may filter the speculative discrepancy values down to a list of potentially valid discrepancy values that may be used by the enhanced ELP circuit to generate an enhanced ELP.Type: ApplicationFiled: January 27, 2017Publication date: August 2, 2018Inventors: Chris Michael Brueggen, Ron M. Roth
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Publication number: 20180212625Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a list decode circuit may include a syndrome calculation circuit, a symbol erasure circuit, an erasure syndrome calculation circuit and a Berlekamp-Massey algorithm circuit (BMA), and an error locator polynomial (ELP) evaluation circuit. The syndrome calculation circuit may calculate a baseline syndrome and erasure syndrome calculation circuit may calculate erasure syndromes from error locator polynomials calculated by the symbol erasure circuit. The BMA circuit may use the calculated syndromes to generate a series of ELPs, which may be used by the ELP evaluation circuit to identify error locations in a codeword.Type: ApplicationFiled: January 26, 2017Publication date: July 26, 2018Inventor: Chris Michael Brueggen
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Publication number: 20170249223Abstract: According to an example, data corruption and single point of failure is prevented in a fault-tolerant memory fabric with multiple redundancy controllers by granting, by a parity media controller, a lock of a stripe to a redundancy controller to perform a sequence on the stripe. The lock may be broken in response to determining a failure of the redundancy controller prior to completing the sequence. In response to breaking the lock, the parity cacheline of the stripe may be flagged as invalid. Also, a journal may be updated to document the breaking of the lock.Type: ApplicationFiled: January 30, 2015Publication date: August 31, 2017Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Derek Alan SHERLOCK, Harvey RAY, Chris Michael BRUEGGEN
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Publication number: 20170199785Abstract: Example implementations relate to a memory controller. For example, an apparatus includes a data storage device and a memory controller coupled to the data storage device. The memory controller is to perform, during a memory scrubbing operation, a corrective action to correct an error associated with a data block stored in the data storage device. The memory control is to determine, during the memory scrubbing operation, whether the corrective action is successful. In response to a determination that the corrective action is a failed corrective action, the memory controller is to fix a hardware failure of the data storage device based on a type of the hardware failure.Type: ApplicationFiled: July 1, 2014Publication date: July 13, 2017Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Gregg B. Lesartre, Chris Michael Brueggen, Lidia Warnes