Patents by Inventor Chris Nassar

Chris Nassar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250251451
    Abstract: Embodiments disclose a system for testing a micro-electromechanical-system (MEMS) switch under hot switching conditions. The system includes a processor, and an instruction memory with computer code instructions stored thereon, configured to cause the system cyclically open and close while a voltage is applied to at least one contact of the MEMS switch. The system measures and stores in a characteristic memory one or more characteristic values associated with the MEMS switch during the cyclical opening and closing. The system records an operational status of the MEMS switch during one or more cycles of the MEMS switch being opened and closed. The operational status of the MEMS switch is either an operational state or a failure state. The system then calculates a life expectancy of the MEMS switch utilizing the measured characteristic values associated with the MEMS switch and the operational status of the MEMS switch.
    Type: Application
    Filed: February 1, 2024
    Publication date: August 7, 2025
    Inventors: Maxwell Connor de Feijter, Chris Nassar
  • Publication number: 20250253102
    Abstract: Systems, devices, and methods of controlling a MEMS switch are disclosed. Aspects of this disclosure are directed towards tailoring the turn-on waveform shape, and/or the turn-off waveform shape, of the control signal that is applied to the MEMS switch. The new waveforms may slow down the beam dynamic to eliminate bouncing upon closing and may dampen the dynamic oscillation of the beam after opening.
    Type: Application
    Filed: February 1, 2024
    Publication date: August 7, 2025
    Inventors: Maja Harfman Todorovic, Chris Nassar, Nicholas Guy Yost
  • Patent number: 12365579
    Abstract: A micro-relay switch array may comprise an array of micro-relays disposed on a substrate, and a cap disposed over the array of micro-relays, thereby encapsulating the array of micro-relays. The micro-relay switch array may further comprise an array of through-substrate vias (TSVs) associated with the array of micro-relays, arranged such that columns of TSVs alternate with columns of micro-relays, and a plurality of device electrical conductors, each of which electrically couples one of the TSVs of the array of TSVs directly to at least two of the micro-relays. The micro-relay switch array may further comprise a plurality of TSV electrical conductors, each of which electrically couples at least two TSVs together. Each micro-relay of the array of micro-relays may be a micro-electromechanical system (MEMS) switch. The substrate and cap may be glass, and the TSVs may be through-glass vias.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: July 22, 2025
    Assignee: Menlo Microsystems, Inc.
    Inventors: Xu Zhu, Hajime Terazawa, Chris Nassar
  • Publication number: 20240409397
    Abstract: A method of preventing corrosion associated with an electrically-conductive through-glass via (TGV) may comprise forming a TGV in a glass substrate for use in a microelectromechanical system (MEMS) device. The TGV has a first end and a second end, and at least partially comprises copper. The method may further comprise applying a conductive barrier layer on the first end of the TGV and/or the second end of the TGV, and applying a metal layer over the conductive barrier layer. The method may further comprise extending the conductive barrier layer over the first end of the TGV, and over at least a portion of the glass substrate encompassing the end of the TGV, such that the conductive barrier layer overlaps a boundary between the TGV and the glass substrate.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Inventors: Christopher F. Keimel, Chris Nassar, Aric Shorey, Matthew Strohmayer
  • Publication number: 20230202831
    Abstract: A micro-relay switch array may comprise an array of micro-relays disposed on a substrate, and a cap disposed over the array of micro-relays, thereby encapsulating the array of micro-relays. The micro-relay switch array may further comprise an array of through-substrate vias (TSVs) associated with the array of micro-relays, arranged such that columns of TSVs alternate with columns of micro-relays, and a plurality of device electrical conductors, each of which electrically couples one of the TSVs of the array of TSVs directly to at least two of the micro-relays. The micro-relay switch array may further comprise a plurality of TSV electrical conductors, each of which electrically couples at least two TSVs together. Each micro-relay of the array of micro-relays may be a micro-electromechanical system (MEMS) switch. The substrate and cap may be glass, and the TSVs may be through-glass vias.
    Type: Application
    Filed: June 9, 2022
    Publication date: June 29, 2023
    Inventors: Xu Zhu, Hajime Terazawa, Chris Nassar
  • Patent number: 11676872
    Abstract: A through-glass via (TGV) formed in a glass substrate may comprise a metal plating layer formed in the TGV. The TGV may have a three-dimensional (3D) topology through the glass substrate and the metal plating layer conformally covering the 3D topology. The TGV may further comprise a barrier layer disposed over the metal plating layer, and a metallization layer disposed over the barrier layer. The metallization layer may be electrically coupled to the metal plating layer through the barrier layer. The barrier layer may comprise a metal-nitride film disposed on the metal plating layer that is electrically coupled to the metallization layer. The barrier layer may comprise a metal film disposed over the metal plating layer and over a portion of glass surrounding the TGV, and an electrically-insulating film disposed upon the metal film, the electrically-insulating film completely overlapping the metal plating layer and partially overlapping the metal film.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: June 13, 2023
    Assignee: MENLO MICROSYSTEMS, INC.
    Inventors: Jaeseok Jeon, Christopher F. Keimel, Chris Nassar, Andrew Minnick
  • Publication number: 20210391228
    Abstract: A through-glass via (TGV) formed in a glass substrate may comprise a metal plating layer formed in the TGV. The TGV may have a three-dimensional (3D) topology through the glass substrate and the metal plating layer conformally covering the 3D topology. The TGV may further comprise a barrier layer disposed over the metal plating layer, and a metallization layer disposed over the barrier layer. The metallization layer may be electrically coupled to the metal plating layer through the barrier layer. The barrier layer may comprise a metal-nitride film disposed on the metal plating layer that is electrically coupled to the metallization layer. The barrier layer may comprise a metal film disposed over the metal plating layer and over a portion of glass surrounding the TGV, and an electrically-insulating film disposed upon the metal film, the electrically-insulating film completely overlapping the metal plating layer and partially overlapping the metal film.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 16, 2021
    Inventors: Jaeseok Jeon, Christopher F. Keimel, Chris Nassar, Andrew Minnick
  • Patent number: 8736013
    Abstract: In one general aspect, an apparatus includes a metal or metal silicide contact layer disposed on an n-well region of a semiconductor substrate to form a primary Schottky diode. The apparatus includes a p-well guard ring region of the semiconductor substrate abutting the primary Schottky diode. The metal silicide contact layer has a perimeter portion extending over the p-well guard ring region of the semiconductor substrate and the p-well guard ring region has a doping level establishing a work function difference relative to the perimeter portion of the metal silicide contact layer to form a guard ring Schottky diode. The guard ring Schottky diode is in series with a p-n junction interface of the p-well region and the n-well region and the guard ring Schottky diode has a polarity opposite to that of the primary Schottky diode.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: May 27, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Chris Nassar, Dan Hahn, Sunglyong Kim, Jongjib Kim
  • Publication number: 20130277791
    Abstract: In one general aspect, an apparatus includes a metal or metal silicide contact layer disposed on an n-well region of a semiconductor substrate to form a primary Schottky diode. The apparatus includes a p-well guard ring region of the semiconductor substrate abutting the primary Schottky diode. The metal silicide contact layer has a perimeter portion extending over the p-well guard ring region of the semiconductor substrate and the p-well guard ring region has a doping level establishing a work function difference relative to the perimeter portion of the metal silicide contact layer to form a guard ring Schottky diode. The guard ring Schottky diode is in series with a p-n junction interface of the p-well region and the n-well region and the guard ring Schottky diode has a polarity opposite to that of the primary Schottky diode.
    Type: Application
    Filed: April 19, 2012
    Publication date: October 24, 2013
    Inventors: Chris Nassar, Dan Hahn, Sunglyong Kim, Jongjib Kim