Abstract: Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory. High error rate format may be MLC format and programming in the high error rate format may program both lower page and upper page data together in a full sequence programming scheme that is suitable for handling high data volume.

Abstract: Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory.

Abstract: In a nonvolatile memory array in which a NAND string includes a back gate that has a charge storage element, the threshold voltage of the back gate is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range.

Abstract: Data that is stored in a higher error rate format in a 3-D nonvolatile memory is backed up in a lower error rate format. Later, the higher error rate copy is sampled to determine if it is acceptable. A sampling pattern samples all word lines of a string and at least one word line of each string of the block.

Abstract: Portions of data stored in a three dimensional memory array are selected based on their locations for calculation of redundancy data. Locations are selected so that no two portions in a set of portions for a given calculation are likely to become uncorrectable at the same time. Selected portions may be separated by at least one word line and separated by at least one string in a block.

Abstract: When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit.

Abstract: Charge leakage from a floating gate in a NAND flash memory die is reduced by applying a data retention bias to a word line extending over the floating gates. The data retention bias is applied to one or more selected word lines when the memory die is in idle mode, when no read, write, erase, or other commands are being executed in the memory die.

Abstract: In a multi-level cell memory array, a flag that indicates that a logical page is unwritten is subject to a two-step verification. In a first verification step, the logical page is read, and ECC decoding is applied. If the first verification step indicates that the logical page is unwritten, then a second verification step counts the number of cells that are not in an unwritten condition.

Abstract: A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.

Abstract: A multi-plane non-volatile memory die includes circuits that receive and apply different parameters to different planes while accessing planes in parallel so that different erase blocks are accessed using individualized parameters. Programming parameters, and read parameters can be modified on a block-by-block basis with modification based on the number of write-erase cycles or other factors.

Abstract: In a multi-level cell (MLC) nonvolatile memory array, data is assigned sequentially to the lower and upper page of a word line, then both lower and upper pages are programmed together before programming a subsequent word line. Word lines of multiple planes are programmed together using latches to hold data until all data is transferred. Tail-ends of data of write commands are stored separately.

Abstract: Configurable parameters may be used to access NAND flash memory according to schemes that optimize such parameters according to predicted characteristics of memory cells, for example, as a function of certain memory cell device geometry, which may be predicted based on the location of a particular device within a memory array.

Abstract: In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings.

Abstract: In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range.

Abstract: A multi-plane non-volatile memory die includes circuits that receive and apply different parameters to different planes while accessing planes in parallel so that different erase blocks are accessed using individualized parameters. Programming parameters, and read parameters can be modified on a block-by-block basis with modification based on the number of write-erase cycles or other factors.

Abstract: A Multi Level Cell (MLC) nonvolatile memory is tested and, if it fails to meet an MLC specification, is reconfigured for operation as an SLC memory by assigning two of the MLC memory cell states as SLC states in a first SLC mode, according to predefined sets of criteria. Subsequently, different MLC memory cell states are assigned as SLC states in a second SLC mode.

Abstract: In a non-volatile memory device, the parameters used in write and erase operation are varied based upon device age. For example, in a programming operation using a staircase waveform, the amplitude of the initial pulse can be adjusted based upon the number of erase-program cycles (hot count) of the block containing the selected physical page for the write. This arrangement can preserve performance for relatively fresh devices, while extending life as a devices ages by using gentler waveforms as the device ages.

Abstract: In a nonvolatile NAND memory array, a NAND block may be falsely determined to be in an erased condition because of the effect of unwritten cells prior to the erase operation. Such cells may be programmed with dummy data prior to erase, or parameters used for a verify operation may be modified to compensate for such cells. Read operations may be similarly modified to compensate for unwritten cells.

Abstract: In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is scrubbed according to a scheme which weights particular data that is exposed to potentially damaging voltages. Data that may cause damage to other data is moved to a location where such potential damage is reduced.

Abstract: Configurable parameters may be used to access NAND flash memory according to schemes that optimize such parameters according to predicted characteristics of memory cells, for example, as a function of certain memory cell device geometry, which may be predicted based on the location of a particular device within a memory array.