Abstract: A ringing signal control circuit used in a Subscriber Line Interface Circuit (SLIC) for connecting a ringing signal bus to a subscriber loop. The ringing signal bus transmits ringing signals along the subscriber loop to a subscriber instrument. The SLIC includes a High Voltage Line Interface (HVLI) circuit connected to the subscriber loop and the ringing signal bus is connected to a ringing generator that provides a source of ringing signals. The ringing signal control circuit comprises a logic interface circuit connected via an address/data bus to a central controller that is arranged to receive ringing connection signals from the central controller and to generate a ringing activation signal. A ring timing circuit receives the ringing activation signal and generates a first and second output signals. The second output signal is transmitted from the ring timing circuit at a specific time interval subsequent to the first output signal.

Abstract: An over-current verifier circuit used in a Subscriber Line Interface Circuit (SLIC) for validating an over-current condition on a subscriber loop comprising a first counter connected to the SLIC disposed to receive an oversense signal from the SLIC. The first counter begins counting when the oversense signal is received and produces an output signal when the oversense signal is still active after the counter finishes, denoting a dc over-current in the subscriber loop. A timer circuit connected to the SLIC also receives the oversense signal. The timer is arranged to begin counting when the oversense signal is received. A second counter further receives the oversense signal and is advanced by one count on the high to low transition of the oversense signal. The second counter produces an output signal when three counter advances are produced before the timer times out, denoting an ac over-current condition.