Abstract: A controller for a phase change memory forms a dedicated burst write partition in the phase change memory and initializes memory cells of the dedicated burst write partition to a SET state. Programming of selected memory cells in the dedicated burst write partition is carried out using only RESET pulses.

Abstract: A controller for a phase change memory forms a dedicated burst write partition in the phase change memory and initializes memory cells of the dedicated burst write partition to a SET state. Programming of selected memory cells in the dedicated burst write partition is carried out using only RESET pulses.

Abstract: Technology is described for reversible resistivity memory having a crystalline silicon bit line. In one aspect, a memory structure comprises a hollow pillar of crystalline silicon inside of reversible resistivity material. The crystalline silicon may serve as a bit line. The memory structure may further comprise conductive material that forms word lines coupled to the outer surface of the reversible resistivity material. A memory cell comprises a portion of the reversible resistivity material between the crystalline silicon and one of the word lines. In one aspect, the hollow pillar of crystalline silicon surrounds a gate oxide, which surrounds a conductive transistor gate. Thus, the hollow pillar of crystalline silicon may function as a channel of a transistor. In one aspect, the crystalline silicon has predominantly a (100) orientation with respect to an inner surface of the reversible resistivity material. In one aspect, the crystalline silicon is a single crystal.

Abstract: A method of forming edge metal lines to interconnect features in a semiconductor device. One embodiment comprises the steps of: patterning a first insulating layer to form a first feature having a first sidewall; depositing a metal layer over the first feature; and etching the metal layer so that a first edge metal line is formed adjacent to the first sidewall. The edge metal line may be substantially anisotropically etched to form the edge metal line. The edge metal line may comprise a plurality of metal layers. The edge metal line may also interconnect features in a semiconductor device (e.g., contacts). The method may further comprise the step of forming a protective coating over a portion of the metal layer such that the etching step may form a metal interconnect line and the edge metal line from the same metal layer. The metal interconnect line may comprise a bus that may have more current carrying capacity than the edge metal line.