Abstract: A method and apparatus for controlling uplink signal power in a distributed antenna system 10 having a master unit 22 and a plurality of remote units 14 and coupled with a base station 12 includes monitoring a noise condition of the distributed antenna system. The invention dynamically adjusts an uplink gain within the distributed antenna system 10 that is applied to uplink signals to a base station 12, based on the monitored noise condition. Monitoring the noise condition in the distributed antenna system 10 includes monitoring one or more remote units 14 of the plurality of remote units and determining if the remote unit is active status or mute status and then. The uplink gain is increased in response to a decrease in the number of remote units that are active status and decreased in response to an increase in the number of remote units that are active status.

Abstract: A PoE powered device and method of operation are provided. The device includes a first port unit configured to negotiate receipt of a level of PoE power from a power sourcing equipment. The power is received on a first pair of taps on a first communication port. A detection unit is configured to detect a presence of a first optional circuit load and to detect a presence of a second optional power load. A control circuit is configured to establish connectivity between a second pair of taps on the first communication port and a second powered device port unit in response to the detection unit detecting the first optional load, and further configured to establish connectivity between the second pair of taps and a third pair of taps on a pass-through communication port in response to the detection unit failing to detect the first load and detecting the second load.

Abstract: Embodiments of the invention provide a method, distributed antenna system, and components that generate a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium. The method comprises receiving a modulated signal that includes the encoded binary data stream and extracting the encoded binary data stream. The method further comprises generating a recovered clock signal that is phase locked to the encoded binary data stream, generating an error signal based on a difference between a phase of the encoded binary data stream and the recovered clock signal, and integrating the error signal to generate a signal to control a voltage controlled oscillator. The method further comprises generating a stable recovered clock signal and producing at least one output clock by scaling the stable recovered clock signal frequency.

Abstract: A distributed antenna system having improved data transmission features incorporates endpoints of the system, which are coupled together by serial data link. At the endpoints, processing may occur utilizing processing circuitry to determine similarities between multiple signal streams. If the streams are similar, the data sent over the serial digital link is reduced by only sending one of the representative signals. In an alternative embodiment of the invention, the difference between the signals might be sent as well. Alternatively, all signals might be sent, but may be compressed with compression circuitry before the signals are transmitted over the serial link. At the endpoint of the system, the signals are reconstructed for further processing and transmission.

Abstract: An apparatus for repeating signals includes a receive antenna for receiving input signals, processing circuitry for processing the input signals to form repeated signals, and a transmit antenna for transmitting the repeated signals. The processing circuitry includes an adaptive digital filter configured to generate cancellation signals that are added to the input signals to cancel unwanted feedback signals from the input signals. A frequency shifting circuit adds a frequency shift to the input signals, after the addition of the cancellation signals, to form repeated signals that are frequency shifted from the input signals. A digital signal processor is coupled to the adaptive digital filter for digitally adapting the filter. The digital signal processor utilizes the frequency shift of the transmission signals to adapt the adaptive digital filter.

Abstract: An apparatus for repeating signals includes a receive antenna for receiving input signals, processing circuitry for processing the input signals to form repeated signals, and a transmit antenna for transmitting the repeated signals. The processing circuitry includes an adaptive digital filter configured to generate cancellation signals that are added to the input signals to cancel unwanted feedback signals from the input signals. A frequency shifting circuit adds a frequency shift to the input signals, after the addition of the cancellation signals, to form repeated signals that are frequency shifted from the input signals. A digital signal processor is coupled to the adaptive digital filter for digitally adapting the filter. The digital signal processor utilizes the frequency shift of the transmission signals to adapt the adaptive digital filter.

Abstract: An apparatus for repeating signals includes a receive antenna for receiving input signals, processing circuitry for processing the input signals to form repeated signals, and a transmit antenna for transmitting the repeated signals. The processing circuitry includes an adaptive digital filter configured to generate cancellation signals that are added to the input signals to cancel unwanted feedback signals from the input signals. A frequency shifting circuit adds a frequency shift to the input signals, after the addition of the cancellation signals, to form repeated signals that are frequency shifted from the input signals. A digital signal processor is coupled to the adaptive digital filter for digitally adapting the filter. The digital signal processor utilizes the frequency shift of the transmission signals to adapt the adaptive digital filter.

Abstract: An apparatus for repeating signals includes a receive antenna for receiving input signals, processing circuitry for processing the input signals to form repeated signals, and a transmit antenna for transmitting the repeated signals. The processing circuitry includes an adaptive digital filter configured to generate cancellation signals that are added to the input signals to cancel unwanted feedback signals from the input signals. A frequency shifting circuit adds a frequency shift to the input signals, after the addition of the cancellation signals, to form repeated signals that are frequency shifted from the input signals. A digital signal processor is coupled to the adaptive digital filter for digitally adapting the filter. The digital signal processor utilizes the frequency shift of the transmission signals to adapt the adaptive digital filter.

Abstract: A PoE powered device and method of operation are provided. The device includes a first port unit configured to negotiate receipt of a level of PoE power from a power sourcing equipment. The power is received on a first pair of taps on a first communication port. A detection unit is configured to detect a presence of a first optional circuit load and to detect a presence of a second optional power load. A control circuit is configured to establish connectivity between a second pair of taps on the first communication port and a second powered device port unit in response to the detection unit detecting the first optional load, and further configured to establish connectivity between the second pair of taps and a third pair of taps on a pass-through communication port in response to the detection unit failing to detect the first load and detecting the second load.

Abstract: Embodiments of the invention provide a method, distributed antenna system, and components that generate a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium. The method comprises receiving a modulated signal that includes the encoded binary data stream and extracting the encoded binary data stream. The method further comprises generating a recovered clock signal that is phase locked to the encoded binary data stream, generating an error signal based on a difference between a phase of the encoded binary data stream and the recovered clock signal, and integrating the error signal to generate a signal to control a voltage controlled oscillator. The method further comprises generating a stable recovered clock signal and producing at least one output clock by scaling the stable recovered clock signal frequency.

Abstract: An apparatus for repeating signals includes a receive antenna for receiving input signals, processing circuitry for processing the input signals to form repeated signals, and a transmit antenna for transmitting the repeated signals. The processing circuitry includes an adaptive digital filter configured to generate cancellation signals that are added to the input signals to cancel unwanted feedback signals from the input signals. A frequency shifting circuit adds a frequency shift to the input signals, after the addition of the cancellation signals, to form repeated signals that are frequency shifted from the input signals. A digital signal processor is coupled to the adaptive digital filter for digitally adapting the filter. The digital signal processor utilizes the frequency shift of the transmission signals to adapt the adaptive digital filter.