Abstract: An apparatus having one or more of a plurality of circuits in a first level of a hierarchy and two or more of the circuits in a second level of the hierarchy is disclosed. The circuits are configured to (i) allocate a profile from the first level down to the second level, (ii) manage from the second level a respective power consumed by each of a plurality of blocks based on the profile and (iii) maintain a sum of the powers approximately constant by increasing the power consumed by a first of the blocks while decreasing the power consumed by a second of the blocks.

Abstract: A cage that is received with a Personal Computer (PC) enclosure in the same manner a peripheral can be received within the PC. The cage is provided with fans, circuitry, connectors and structural features to create a ATCA or MicroTCA type environment required for the operation of an AMC card. The cage features a lateral connector for connecting to the motherboard and transferring PCI-Express protocolized signals between the cage and the CPU. The cage also features means to receive and support an AMC card within the ATCA and MicroTCA environment created for it by the cage. In this configuration, the CPU can communicate with the AMC card using the PCI-Express interconnect protocol as if the AMC card is another peripheral I/O device. In this manner, an advanced form factor AMC card may be tested and used within a PC environment suitable only for conventional form factor expansion cards and peripheral I/O devices.

Abstract: A direct memory access (DMA) controller transmits and receives formatted data frames having frame headers in a communications subsystem. The DMA controller includes a transmit input and output, a receive input and output, transmit circuitry, receive circuitry, a receive frame header capture circuit, a receive frame action table and a response message table. The transmit circuitry receives transmit data frames on the transmit input and applies the transmit data frames to the transmit output. The receive circuitry receives receive data frames on the receive input and applies the receive data frames to the receive output. The receive frame header capture circuit obtains a frame header from the received data frames and applies the frame header to the receive frame action table. The receive frame action table generates a frame action command based on the frame header field.