Abstract: In various embodiments a solar cell may include a solar cell wafer substrate made of silicon having a major share of mono crystalline structure with {111} crystal plane parallel to one wafer edge; a dielectric layer disposed over the backside of solar cell wafer substrate; a plurality of contact openings extending through the dielectric layer to the solar cell wafer substrate; a plurality of metal contacts formed in the plurality of contact openings; and a metal layer disposed over the dielectric layer; wherein the metal layer is electrically coupled to the solar cell wafer substrate by means of the plurality of metal contacts; wherein at least one contact opening of the plurality of contact openings extends non parallel to {111} crystal plane.

Abstract: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

Abstract: In various embodiments, an electrical subpanel system is disclosed. The subpanel system may include a DC/AC inverter configured to accept a DC electrical input and to provide an auxiliary AC current output; a quick-disconnect coupling, a busbar connected between the auxiliary AC current output and the quick-disconnect coupling, a receptacle for connecting to at least one electrical device coupled in parallel to said busbar, where the quick-disconnect coupling may be configured to be selectively connected to a mains branch circuit current.

Abstract: In various embodiments, an electrical subpanel system is disclosed. The subpanel system may include a DC/AC inverter configured to accept a DC electrical input and to provide an auxiliary AC current output; a quick-disconnect coupling, a busbar connected between the auxiliary AC current output and the quick-disconnect coupling, a receptacle for connecting to at least one electrical device coupled in parallel to said busbar, where the quick-disconnect coupling may be configured to be selectively connected to a mains branch circuit current.

Abstract: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

Abstract: In various embodiments a solar cell may include a solar cell wafer substrate made of silicon having a major share of mono crystalline structure with {111} crystal plane parallel to one wafer edge; a dielectric layer disposed over the backside of solar cell wafer substrate; a plurality of contact openings extending through the dielectric layer to the solar cell wafer substrate; a plurality of metal contacts formed in the plurality of contact openings; and a metal layer disposed over the dielectric layer; wherein the metal layer is electrically coupled to the solar cell wafer substrate by means of the plurality of metal contacts; wherein at least one contact opening of the plurality of contact openings extends non parallel to {111} crystal plane.

Abstract: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

Abstract: A solar power unit having a solar module with a frame defining a planar solar collection area, a photovoltaic cell mounted within said area, a junction box electrically connected to at least one of said photovoltaic cells; and a support structure fixable to said solar module having a first leg set comprising a first upper leg and a first lower leg, the leg set securing the solar module on a surface at an angle.

Abstract: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. A preferred embodiment includes forming at least one trench in a workpiece, and forming a thin nitride liner over sidewalls and a bottom surface of the at least one trench and over a top surface of the workpiece using atomic layer deposition (ALD). An insulating material is deposited over the top surface of the workpiece, filling the at least one trench. At least a portion of the insulating material is removed from over the top surface of the workpiece. After removing the at least a portion of insulating material from over the top surface of the workpiece, the thin nitride liner in the at least one trench is at least coplanar with the top surface of the workpiece. The thin nitride liner and the insulating material form an isolation region of the semiconductor device.

Abstract: A solar simulator is disclosed having a test chamber for receiving a photovoltaic device for testing, an illumination source for selectively illuminating the photovoltaic device to produce a test signal therefrom, a spectrophotometer for providing a measurement of the spectral distribution of the output of the illumination source, a database containing spectral response information of monitor cell, reference device and DUT, and a computation device for receiving said test signal and said measurement, wherein the computation device converts said test signal into a test value based on said measurement.

Abstract: In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

Abstract: In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms.

Abstract: A fin-shaped structure is formed from a semiconductor material. The fin-shaped structure is processed to generate a tensile strain within the semiconductor material along a longitudinal direction of the fin.

Abstract: A method for fabricating a semiconductor device including implanting a selected material at a desired target depth below a surface of a silicon substrate, performing an annealing process to create a band of precipitates formed from the selected material and the silicon of the silicon substrate at the desired target depth, and forming a source region and a drain region in the substrate such that a channel region there between is positioned above the band of precipitates, wherein the desired target depth is such that a desired separation distance is achieved between the channel region and the band of precipitates, and wherein an average lattice constant of the band of precipitates is different from the average lattice constant of the silicon substrate so as to cause a stress in the channel region.

Abstract: In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

Abstract: In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

Abstract: In an embodiment of the invention, an amorphous phase dielectric material is selectively formed over a substrate. The amorphous phase dielectric material is then converted into a crystalline phase dielectric material.

Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device is provided. The method includes: forming a semiconductor structure; forming a stress liner over the semiconductor structure; and changing the stress properties of at least a part of the stress liner.

Abstract: A fin-shaped structure is formed from a semiconductor material. The fin-shaped structure is processed to generate a tensile strain within the semiconductor material along a longitudinal direction of the fin.

Abstract: A method for fabricating a semiconductor device including implanting a selected material at a desired target depth below a surface of a silicon substrate, performing an annealing process to create a band of precipitates formed from the selected material and the silicon of the silicon substrate at the desired target depth, and forming a source region and a drain region in the substrate such that a channel region there between is positioned above the band of precipitates, wherein the desired target depth is such that a desired separation distance is achieved between the channel region and the band of precipitates, and wherein an average lattice constant of the band of precipitates is different from the average lattice constant of the silicon substrate so as to cause a stress in the channel region.