Patents by Inventor Chris Yakopcic
Chris Yakopcic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954588Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.Type: GrantFiled: June 30, 2021Date of Patent: April 9, 2024Assignee: University of DaytonInventors: Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
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Patent number: 11907831Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.Type: GrantFiled: December 6, 2022Date of Patent: February 20, 2024Assignee: University of DaytonInventors: Chris Yakopcic, Md Raqibul Hasan, Tarek M. Taha
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Publication number: 20240037380Abstract: An analog neuromphric circuit is disclosed having an input layer, a liquid layer, and an output layer each with resistive memory crossbar configurations to identify a temporal signal for a duration of time. The input layer encodes input layer spiking neurons based on encoding signals generated from input voltages applied an input layer resistive memory crossbar configuration. The liquid layer counts each spike generated by liquid layer spiking neurons for the duration of time based on liquid layer signals generated from the input spiking neuron voltages generated from each input layer spiking neurons applied to a liquid layer resistive memory crossbar configuration. The output layer identifies the temporal signal for the duration of time based on output voltages generated from the counting voltages generated from each count of each spike generated by the liquid layer spiking neurons for the duration of time applied to an output resistive memory crossbar configuration.Type: ApplicationFiled: July 26, 2023Publication date: February 1, 2024Inventors: Alex Henderson, Chris Yakopcic, Tarek M. Taha
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Publication number: 20230409893Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to an input voltage signal as the input voltage signal propagates through the resistive memories generating a first output voltage signal and to provide a resistance to a first error signal that propagates through the resistive memories generating a second output voltage signal. A comparator generates the first error signal that is representative of a difference between the first output voltage signal and the desired output signal and generates the first error signal so that the first error signal propagates back through the plurality of resistive memories. A resistance adjuster adjusts a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal.Type: ApplicationFiled: September 5, 2023Publication date: December 21, 2023Inventors: Tarek M. Taha, Md Raqibul Hasan, Chris Yakopcic
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Patent number: 11748609Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to an input voltage signal as the input voltage signal propagates through the resistive memories generating a first output voltage signal and to provide a resistance to a first error signal that propagates through the resistive memories generating a second output voltage signal. A comparator generates the first error signal that is representative of a difference between the first output voltage signal and the desired output signal and generates the first error signal so that the first error signal propagates back through the plurality of resistive memories. A resistance adjuster adjusts a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal.Type: GrantFiled: January 5, 2021Date of Patent: September 5, 2023Assignee: University of DaytonInventors: Tarek M. Taha, Md Raqibul Hasan, Chris Yakopcic
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Publication number: 20230095626Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.Type: ApplicationFiled: December 6, 2022Publication date: March 30, 2023Inventors: Chris Yakopcic, Raqibul Hasan, Tarek M. Taha
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Publication number: 20230028592Abstract: An analog neuromorphic circuit is disclosed having a resistive memory crossbar configurations positioned in the analog neuromorphic circuit forming a 3D stack. Input voltages are applied to an input selector unit that selects a first selected resistive memory crossbar configuration that the input voltages are applied. Output voltages are generated by the first selected resistive memory crossbar configuration from a propagation of the input voltages through resistive memories positioned on the first selected resistive memory crossbar configuration. An output selector unit selects the first selected resistive memory crossbar configuration that generates the output voltages. Each output voltage corresponds to an output of the first selected resistive memory crossbar configuration as selected by the output selector.Type: ApplicationFiled: July 25, 2022Publication date: January 26, 2023Inventors: B. Rasitha Fernando, Tarek M. Taha, Chris Yakopcic
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Patent number: 11521054Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.Type: GrantFiled: June 29, 2021Date of Patent: December 6, 2022Assignee: University of DaytonInventors: Chris Yakopcic, Md Raqibul Hasan, Tarek M. Taha
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Publication number: 20220027718Abstract: An analog neuromorphic circuit is disclosed having a first and a second memristor crossbar configuration implemented into an autoencoder. The first memristor crossbar configuration includes resistive memories that provide resistance values to each corresponding input voltage applied to the first memristor crossbar configuration to generate first output voltages that are compressed from the input voltages. The second memristor crossbar includes resistive memories that provide resistance values to each corresponding first output voltage applied to the second memristor crossbar configuration to generate second output voltages that are decompressed from the first output voltages. A controller compares the second output voltages to the input voltages to determine if the second output voltages are within a threshold of the input voltages.Type: ApplicationFiled: July 23, 2021Publication date: January 27, 2022Inventors: Md Shahanur Alam, Chris Yakopcic, Tarek M. Taha
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Publication number: 20210326688Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.Type: ApplicationFiled: June 29, 2021Publication date: October 21, 2021Inventors: Chris Yakopcic, Md Raqibul Hasan, Tarek M. Taha
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Publication number: 20210326689Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.Type: ApplicationFiled: June 30, 2021Publication date: October 21, 2021Inventors: Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
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Patent number: 11087208Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.Type: GrantFiled: September 29, 2020Date of Patent: August 10, 2021Assignee: University of DaytonInventors: Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
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Publication number: 20210201125Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to an input voltage signal as the input voltage signal propagates through the resistive memories generating a first output voltage signal and to provide a resistance to a first error signal that propagates through the resistive memories generating a second output voltage signal. A comparator generates the first error signal that is representative of a difference between the first output voltage signal and the desired output signal and generates the first error signal so that the first error signal propagates back through the plurality of resistive memories. A resistance adjuster adjusts a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal.Type: ApplicationFiled: January 5, 2021Publication date: July 1, 2021Inventors: Tarek M. Taha, Md Raqibul Hasan, Chris Yakopcic
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Patent number: 11049003Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.Type: GrantFiled: June 1, 2020Date of Patent: June 29, 2021Assignee: University of DaytonInventors: Chris Yakopcic, Md Raqibul Hasan, Tarek M. Taha
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Publication number: 20210019610Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrixvalues included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in theweighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.Type: ApplicationFiled: September 29, 2020Publication date: January 21, 2021Inventors: Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
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Publication number: 20210019597Abstract: A spiking neural network (SNN) system is disclosed having spiking neurons associated with clause values associated with a satisfiability (SAT) problem. Each spiking neuron generates a voltage spike when on input voltage applied to each spiking neuron is increased above a spiking voltage threshold. The input voltage that is increased above the spiking voltage threshold is indicative that the corresponding clause value is satisfied. A controller applies the clause grid that includes clause values to a literal grid that includes literal values. The controller generates the input voltage that is applied to each spiking neuron based on each corresponding clause value associated with each spiking neuron that is applied to the literal values. The controller determines that each clause value is satisfied when the corresponding spiking neuron generates the voltage spike and that each clause value is unsatisfied when the corresponding spiking neuron fails to generate the voltage spike.Type: ApplicationFiled: July 20, 2020Publication date: January 21, 2021Inventors: Chris Yakopcic, Tarek M. Taha
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Patent number: 10885429Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to an input voltage signal as the input voltage signal propagates through the resistive memories generating a first output voltage signal and to provide a resistance to a first error signal that propagates through the resistive memories generating a second output voltage signal. A comparator generates the first error signal that is representative of a difference between the first output voltage signal and the desired output signal and generates the first error signal so that the first error signal propagates back through the plurality of resistive memories. A resistance adjuster adjusts a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal.Type: GrantFiled: July 6, 2016Date of Patent: January 5, 2021Assignee: University of DaytonInventors: Tarek M. Taha, Raqibul Hasan, Chris Yakopcic
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Publication number: 20200364550Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.Type: ApplicationFiled: June 1, 2020Publication date: November 19, 2020Inventors: Chris Yakopcic, Md Raqibul Hasan, Tarek M. Taha
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Patent number: 10789528Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.Type: GrantFiled: July 9, 2019Date of Patent: September 29, 2020Assignee: University of DaytonInventors: Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
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Patent number: 10671914Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.Type: GrantFiled: November 11, 2019Date of Patent: June 2, 2020Assignee: University of DaytonInventors: Chris Yakopcic, Md Raqibul Hasan, Tarek M. Taha