Patents by Inventor Chris Yip
Chris Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230130602Abstract: Provided herein are compounds, compositions, and methods useful for reducing, preventing, and/or inhibiting germination of C. difficile spores, including methods for inhibiting C. difficile germination to prevent or treating C. difficile-associated diseases and disorders such as, for example, severe diarrhea and colitis in a subject. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present invention.Type: ApplicationFiled: September 9, 2022Publication date: April 27, 2023Inventors: Ernesto Abel-Santos, Steven Firestine, Shiv Sharma, Angel Schilke, Chris Yip, Jacqueline Phan
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Patent number: 10936415Abstract: An error correction scheme in flash memory. Methods include extending a lifetime of a memory block, including: receiving an indication that an error occurred during a write operation at a first location in a memory block, the first location associated with a faulty page of the memory block; and performing a modified exclusive OR (XOR) scheme on the memory block by: performing a de-XOR operation that generates recovery data of the faulty page; storing the recovery data in a location different from the faulty page of memory; marking the faulty page for exclusion in future de-XOR operations; and performing a parity calculation that generates an updated parity value that includes all pages of the memory block that have been programmed except for the faulty page.Type: GrantFiled: June 28, 2019Date of Patent: March 2, 2021Assignee: Western Digital Technologies, Inc.Inventors: Chris Yip, Piyush Sagdeo, Gautam Dusija, Vidhu Gupta
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Publication number: 20200409787Abstract: An error correction scheme in flash memory. Methods include extending a lifetime of a memory block, including: receiving an indication that an error occurred during a write operation at a first location in a memory block, the first location associated with a faulty page of the memory block; and performing a modified exclusive OR (XOR) scheme on the memory block by: performing a de-XOR operation that generates recovery data of the faulty page; storing the recovery data in a location different from the faulty page of memory; marking the faulty page for exclusion in future de-XOR operations; and performing a parity calculation that generates an updated parity value that includes all pages of the memory block that have been programmed except for the faulty page.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Applicant: Western Digital Technologies, Inc.Inventors: Chris Yip, Piyush Sagdeo, Gautam Dusija, Vidhu Gupta
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Patent number: 10790031Abstract: A data storage system performs operations including receiving a data read command corresponding to a first memory cell; determining whether the first memory cell is in a first read condition; if the first memory cell is in the first read condition: applying a first voltage level to the first memory cell, the first voltage level being a predetermined voltage level corresponding to a read operation for memory cells in the first read condition; and sensing a first level of current, or lack thereof, through the first memory cell during application of the first voltage level to the first memory cell; and if the first memory cell is not in the first read condition: applying a second voltage level to the first memory cell, the second voltage level being a voltage level corresponding to a read operation for memory cells in a read condition other than the first read condition.Type: GrantFiled: June 5, 2019Date of Patent: September 29, 2020Assignee: Western Digital Technologies, Inc.Inventors: Piyush Sagdeo, Chris Yip, Sourabh Sankule, Pitamber Shukla, Anubhav Khandelwal, Mohan Dunga, Niles Yang
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Patent number: 10691372Abstract: Techniques are provided for maintaining threshold voltages of non-data transistors in a memory device. The memory device has a stack comprising alternating horizontal conductive layers and horizontal dielectric layers. A control circuit is configured to test a threshold voltage criterion of non-data transistors in response to a trigger condition being met with respect to an erase of a data memory cells in a first tier of the stack. The control circuit is configured move valid data out of a data memory cells in a second tier of the stack in response to a determination that the threshold voltage criterion is not met. The control circuit is configured to adjust threshold voltages of the non-data transistors after moving the valid data out of the second set of data memory cells such that the threshold voltage criterion is met.Type: GrantFiled: December 7, 2018Date of Patent: June 23, 2020Assignee: Western Digital Technologies, Inc.Inventors: Srinivasan Seetharaman, Piyush Sagdeo, Sourabh Sankule, Chris Yip
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Publication number: 20200183610Abstract: Techniques are provided for maintaining threshold voltages of non-data transistors in a memory device. The memory device has a stack comprising alternating horizontal conductive layers and horizontal dielectric layers. A control circuit is configured to test a threshold voltage criterion of non-data transistors in response to a trigger condition being met with respect to an erase of a data memory cells in a first tier of the stack. The control circuit is configured move valid data out of a data memory cells in a second tier of the stack in response to a determination that the threshold voltage criterion is not met. The control circuit is configured to adjust threshold voltages of the non-data transistors after moving the valid data out of the second set of data memory cells such that the threshold voltage criterion is met.Type: ApplicationFiled: December 7, 2018Publication date: June 11, 2020Applicant: Western Digital Technologies, Inc.Inventors: Srinivasan Seetharaman, Piyush Sagdeo, Sourabh Sankule, Chris Yip
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Patent number: 10068656Abstract: A non-volatile memory system implements a multi-pass programming process that includes separately programming groups of memory cells in a common block by performing programming for memory cells that are connected to two adjacent word lines and are part of a first group of memory cells followed by performing programming for other memory cells that are also connected to the two adjacent word lines and are part of a second group of memory cells.Type: GrantFiled: December 27, 2016Date of Patent: September 4, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Deepanshu Dutta, Sarath Puthenthermadam, Chris Yip
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Publication number: 20180182463Abstract: A non-volatile memory system implements a multi-pass programming process that includes separately programming groups of memory cells in a common block by performing programming for memory cells that are connected to two adjacent word lines and are part of a first group of memory cells followed by performing programming for other memory cells that are also connected to the two adjacent word lines and are part of a second group of memory cells.Type: ApplicationFiled: December 27, 2016Publication date: June 28, 2018Applicant: SANDISK TECHNOLOGIES LLCInventors: Deepanshu Dutta, Sarath Puthenthermadam, Chris Yip
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Patent number: 9792998Abstract: Systems and methods for detecting program disturb and for programming/reading based on the detected program disturb are disclosed. Program disturb comprises unintentionally programming an unselected section of memory during the program operation of the selected section of memory. To reduce the effect of program disturb, the section of memory is analyzed in a predetermined state (such as the erase state) for program disturb. In response to identifying signs of program disturb, the voltages used to program the section of memory (such as the program verify levels for programming data into the cells of the section of memory) may be adjusted. Likewise, when reading data from the section of memory, the read voltages may be adjusted based on the adjusted voltages used for programming. In this way, using the adjusted programming and reading voltages, the effect of program disturb may be reduced.Type: GrantFiled: March 29, 2016Date of Patent: October 17, 2017Assignee: SanDisk Technologies LLCInventors: Nian Niles Yang, Chris Yip, Grishma Shah
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Publication number: 20170287568Abstract: Systems and methods for detecting program disturb and for programming/reading based on the detected program disturb are disclosed. Program disturb comprises unintentionally programming an unselected section of memory during the program operation of the selected section of memory. To reduce the effect of program disturb, the section of memory is analyzed in a predetermined state (such as the erase state) for program disturb. In response to identifying signs of program disturb, the voltages used to program the section of memory (such as the program verify levels for programming data into the cells of the section of memory) may be adjusted. Likewise, when reading data from the section of memory, the read voltages may be adjusted based on the adjusted voltages used for programming. In this way, using the adjusted programming and reading voltages, the effect of program disturb may be reduced.Type: ApplicationFiled: March 29, 2016Publication date: October 5, 2017Applicant: SanDisk Technologies, Inc.Inventors: Nian Niles Yang, Chris Yip, Grishma Shah
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Patent number: 9711231Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.Type: GrantFiled: June 24, 2016Date of Patent: July 18, 2017Assignee: SanDisk Technologies LLCInventors: Chris Yip, Philip Reusswig, Nian Niles Yang, Grishma Shah, Abuzer Azo Dogan, Biswajit Ray, Mohan Dunga, Joanna Lai, Changyuan Chen