Abstract: A video decoder system includes a video decoding engine, noise database, artifact estimator and post-processing unit. The video coder may generate recovered video from a data stream of coded video data, which may have visually-perceptible artifacts introduced as a byproduct of compression. The noise database may store a plurality of previously developed noise patches. The artifact estimator may estimate the location of coding artifacts present in the recovered video and select noise patches from the database to mask the artifacts and the post-processing unit may integrate the selected noise patches into the recovered video. In this manner, the video decoder may generate post-processed noise which may mask artifacts that otherwise would be generated by a video coding process.

Abstract: Systems, apparatuses and methods whereby a base coded video signal is provided to a decoder having a set of post-processing stages. The base coded video signal can be decoded to produce a base decoded video signal. Post-processing of the base decoded video signal can be used to produce an enhanced quality video output signal. Application of a post-processing stage can be implemented according to the capabilities of the decoder and/or the instantaneous operating parameters of the decoder and/or characteristics of a display. A control signal, communicated over a dedicated channel separate from the base coded video signal, can be used initiate and/or aid implementation of a post-processing stage. The control signal can also provide information to assist/manage the decoding of the base coded video signal. The use of additional post-processing stages increases the complexity of an overall decoding process while improving the quality of a resulting reproduced video sequence.

Abstract: Methods, systems, and apparatus are presented for reducing distortion in an image, such as a video image. A video image can be captured by an image capture device, e.g. during a video conferencing session. Distortion correction processing, such as the application of one or more warping techniques, can be applied to the captured image to produce a distortion corrected image, which can be transmitted to one or more participants. The warping techniques can be performed in accordance with one or more warp parameters specifying a transformation of the captured image. Further, the warp parameters can be generated in accordance with an orientation of the image capture device, which can be determined based on sensor data or can be a fixed value. Additionally or alternatively, the warp parameters can be determined in accordance with a reference image or model to which the captured image should be warped.

Abstract: Disclosed is an exemplary video coder and video coding method according to an embodiment of the present invention. The exemplary video coder includes a scheduler, a plurality of processors and a multiplexer. The scheduler can examine processing units in an input buffer to determine an order for the processing unit to be coded by a processor. If the processing unit under examination depends on a processing unit not yet processed, the processing unit under examination can be merged with other processing units, if any, that share a similar dependency. If the processing unit under examination does not depend on any processing units not yet processed, it can be sent to a next available processor for coding. When a processing unit is sent to a processor, any merged processing units that depend on sent processing unit can also be sent to a next available processor.

Abstract: This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency field in a load instruction or by a latency specification of a prior instruction. This invention is useful in the great majority of cases where the code can tolerate incremental increases in load latency for a reduction in cache miss penalty.

Abstract: Methods, systems, and apparatus are presented for reducing distortion in an image, such as a video image. A video image can be captured by an image capture device, e.g. during a video conferencing session. Distortion correction processing, such as the application of one or more warping techniques, can be applied to the captured image to produce a distortion corrected image, which can be transmitted to one or more participants. The warping techniques can be performed in accordance with one or more warp parameters specifying a transformation of the captured image. Further, the warp parameters can be generated in accordance with an orientation of the image capture device, which can be determined based on sensor data or can be a fixed value. Additionally or alternatively, the warp parameters can be determined in accordance with a reference image or model to which the captured image should be warped.

Abstract: A video decoder system includes a video decoding engine, noise database, artifact estimator and post-processing unit. The video coder may generate recovered video from a data stream of coded video data, which may have visually-perceptible artifacts introduced as a byproduct of compression. The noise database may store a plurality of previously developed noise patches. The artifact estimator may estimate the location of coding artifacts present in the recovered video and select noise patches from the database to mask the artifacts and the post-processing unit may integrate the selected noise patches into the recovered video. In this manner, the video decoder may generate post-processed noise which may mask artifacts that otherwise would be generated by a video coding process.

Abstract: A programmable graphics pipeline and method for processing multiple partitioned multimedia data, such as graphics data, image data, video data, or audio data. A preferred embodiment of the programmable graphics pipeline includes an instruction cache, a register file, and a vector functional unit that perform partitioned instructions. In addition, an enhanced rasterization unit is used to generate inverse-mapped source coordinates in addition to destination output coordinates for graphics and other media processing. An enhanced texture address unit generates corresponding memory addresses of source texture data for graphics processing and source media data for media processing. Data retrieved from memory are stored in an enhanced texture cache for use by the vector functional unit. A vector output unit includes a blending unit for graphics data and an output buffer for wide media data.

Abstract: Disclosed is an exemplary video coder and video coding method according to an embodiment of the present invention. The exemplary video coder includes a scheduler, a plurality of processors and a multiplexer. The scheduler can examine processing units in an input buffer to determine an order for the processing unit to be coded by a processor. If the processing unit under examination depends on a processing unit not yet processed, the processing unit under examination can be merged with other processing units, if any, that share a similar dependency. If the processing unit under examination does not depend on any processing units not yet processed, it can be sent to a next available processor for coding. When a processing unit is sent to a processor, any merged processing units that depend on sent processing unit can also be sent to a next available processor.

Abstract: This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency field in a load instruction or by a latency specification of a prior instruction. This invention is useful in the great majority of cases where the code can tolerate incremental increases in load latency for a reduction in cache miss penalty.

Abstract: Systems, apparatuses and methods whereby a base coded video signal is provided to a decoder having a set of post-processing stages. The base coded video signal can be decoded to produce a base decoded video signal. Post-processing of the base decoded video signal can be used to produce an enhanced quality video output signal. Application of a post-processing stage can be implemented according to the capabilities of the decoder and/or the instantaneous operating parameters of the decoder and/or characteristics of a display. A control signal, communicated over a dedicated channel separate from the base coded video signal, can be used initiate and/or aid implementation of a post-processing stage. The control signal can also provide information to assist/manage the decoding of the base coded video signal. The use of additional post-processing stages increases the complexity of an overall decoding process while improving the quality of a resulting reproduced video sequence.

Abstract: A boundary macroblock of a video object is padded without significant synchronization overhead between a host processor and an existing coprocessor. The host processor determines horizontal and vertical graphics primitives as a function of shape data stored in a host memory. The shape data determine whether a dot, a line, or a rectangle primitive should be used to pad transparent pixels in the macroblock. The host processor communicates the primitives to a coprocessor, which renders the primitives in an interleaved pipeline fashion to pad transparent pixels of the macroblock based on texture data stored in video memory. The flow of primitives is in one direction from the host processor to the graphics coprocessor, and the texture data is not transferred back and forth between the host processor and coprocessor. This technique is especially useful for enabling acceleration of MPEG-4 video decoding utilizing existing coprocessors capable of accelerating MPEG-1/2 video decoding.

Abstract: A programmable graphics pipeline and method for processing multiple partitioned multimedia data, such as graphics data, image data, video data, or audio data. A preferred embodiment of the programmable graphics pipeline includes an instruction cache, a register file, and a vector functional unit that perform partitioned instructions. In addition, an enhanced rasterization unit is used to generate inverse-mapped source coordinates in addition to destination output coordinates for graphics and other media processing. An enhanced texture address unit generates corresponding memory addresses of source texture data for graphics processing and source media data for media processing. Data retrieved from memory are stored in an enhanced texture cache for use by the vector functional unit. A vector output unit includes a blending unit for graphics data and an output buffer for wide media data.

Abstract: A method for efficiently padding a macroblock of a video object plane employs two new instructions. The instructions, PadToRight and PadToLeft, are applied in alternating sequence during a PadPass 1 operation and a PadPass 2 operation. The results of these two operations are then averaged to pad each transparent pixel in each row of a macroblock that includes at least one opaque pixel. A Shift_in register is used to temporarily store data to facilitate the operation implemented by these instructions. Once the transparent pixels in each row have been padded horizontally, pixels in rows having shape data equal to zero (indicating all pixels in the row are transparent) are padded in a pre-processing step, followed by an upward propagation step. The two instructions are preferably implemented using 2:1 multiplexers implemented with an arithmetic logic unit. The method is particularly useful in set-top boxes, games, and other video applications.

Abstract: A boundary macroblock of a video object is padded without significant synchronization overhead between a host processor and an existing coprocessor. The host processor determines horizontal and vertical graphics primitives as a function of shape data stored in a host memory. The shape data determine whether a dot, a line, or a rectangle primitive should be used to pad transparent pixels in the macroblock. The host processor communicates the primitives to a coprocessor, which renders the primitives in an interleaved pipeline fashion to pad transparent pixels of the macroblock based on texture data stored in video memory. The flow of primitives is in one direction from the host processor to the graphics coprocessor, and the texture data is not transferred back and forth between the host processor and coprocessor. This technique is especially useful for enabling acceleration of MPEG-4 video decoding utilizing existing coprocessors capable of accelerating MPEG-1/2 video decoding.

Abstract: A programmable graphics pipeline and method for processing multiple partitioned multimedia data, such as graphics data, image data, video data, or audio data. A preferred embodiment of the programmable graphics pipeline includes an instruction cache, a register file, and a vector functional unit that perform partitioned instructions. In addition, an enhanced rasterization unit is used to generate inverse-mapped source coordinates in addition to destination output coordinates for graphics and other media processing. An enhanced texture address unit generates corresponding memory addresses of source texture data for graphics processing and source media data for media processing. Data retrieved from memory are stored in an enhanced texture cache for use by the vector functional unit. A vector output unit includes a blending unit for graphics data and an output buffer for wide media data.

Abstract: A method for efficiently padding a macroblock of a video object plane employs two new instructions. The instructions, PadToRight and PadToLeft, are applied in alternating sequence during a PadPass 1 operation and a PadPass 2 operation. The results of these two operations are then averaged to pad each transparent pixel in each row of a macroblock that includes at least one opaque pixel. A Shift_in register is used to temporarily store data to facilitate the operation implemented by these instructions. Once the transparent pixels in each row have been padded horizontally, pixels in rows having shape data equal to zero (indicating all pixels in the row are transparent) are padded in a pre-processing step, followed by an upward propagation step. The two instructions are preferably implemented using 2:1 multiplexers implemented with an arithmetic logic unit. The method is particularly useful in set-top boxes, games, and other video applications.

Abstract: A boundary macroblock of a video object is padded without significant synchronization overhead between a host processor and an existing coprocessor. The host processor determines horizontal and vertical graphics primitives as a function of shape data stored in a host memory. The shape data determine whether a dot, a line, or a rectangle primitive should be used to pad transparent pixels in the macroblock. The host processor communicates the primitives to a coprocessor, which renders the primitives in an interleaved pipeline fashion to pad transparent pixels of the macroblock based on texture data stored in video memory. The flow of primitives is in one direction from the host processor to the graphics coprocessor, and the texture data is not transferred back and forth between the host processor and coprocessor. This technique is especially useful for enabling acceleration of MPEG-4 video decoding utilizing existing coprocessors capable of accelerating MPEG-1/2 video decoding.