Patents by Inventor Christa R. Willets
Christa R. Willets has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9570564Abstract: Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor.Type: GrantFiled: August 5, 2014Date of Patent: February 14, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Deborah A. Alperstein, David L. Harame, Alvin J. Joseph, Qizhi Liu, Keith J. Machia, Christa R. Willets
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Publication number: 20160043203Abstract: Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor.Type: ApplicationFiled: August 5, 2014Publication date: February 11, 2016Inventors: Deborah A. Alperstein, David L. Harame, Alvin J. Joseph, Qizhi Liu, Keith J. Machia, Christa R. Willets
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Patent number: 9231087Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.Type: GrantFiled: April 2, 2015Date of Patent: January 5, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: John J. Benoit, James R. Elliott, Peter B. Gray, Alvin J. Joseph, Qizhi Liu, Christa R. Willets
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Publication number: 20150214344Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.Type: ApplicationFiled: April 2, 2015Publication date: July 30, 2015Inventors: John J. Benoit, James R. Elliott, Peter B. Gray, Alvin J. Joseph, Qizhi Liu, Christa R. Willets
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Patent number: 9059196Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.Type: GrantFiled: November 4, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: John J. Benoit, James R. Elliot, Peter B. Gray, Alvin J. Joseph, Qizhi Liu, Christa R. Willets
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Publication number: 20150123245Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.Type: ApplicationFiled: November 4, 2013Publication date: May 7, 2015Applicant: International Business Machines CorporationInventors: John J. Benoit, James R. Elliott, Peter B. Gray, Alvin J. Joseph, Qizhi Liu, Christa R. Willets
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Patent number: 8846481Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.Type: GrantFiled: December 20, 2013Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Marc W. Cantell, Thai Doan, Jessica A. Levy, Qizhi Liu, William J. Murphy, Christa R. Willets
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Publication number: 20140113426Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.Type: ApplicationFiled: December 20, 2013Publication date: April 24, 2014Applicant: International Business Machines CorporationInventors: Marc W. Cantell, Thai Doan, Jessica A. Levy, Qizhi Liu, William J. Murphy, Christa R. Willets
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Patent number: 8470713Abstract: A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.Type: GrantFiled: December 13, 2010Date of Patent: June 25, 2013Assignee: International Business Machines CorporationInventors: James A. Culp, John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin, Christa R. Willets
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Publication number: 20120313146Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.Type: ApplicationFiled: June 8, 2011Publication date: December 13, 2012Applicant: International Business Machines CorporationInventors: Marc W. Cantell, Thai Doan, Jessica A. Levy, Qizhi Liu, William J. Murphy, Christa R. Willets
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Publication number: 20120149200Abstract: A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.Type: ApplicationFiled: December 13, 2010Publication date: June 14, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James A. Culp, John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin, Christa R. Willets
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Patent number: 6294429Abstract: The present invention relates to a method of forming a charge injection region on a floating gate of a memory cell using an etching process. The present invention defines the sharp corners for electron charge injection region of a floating gate by etching the shape into the floating gate silicon rather than forming the injection point using an oxidation process. By using the etching process of the present invention, limitations on the size of the floating gate are overcome and the memory cell can be formed using the minimum geometry allowed by lithography. This allows further scaling of the cell film thickness than is presently capable and does not limit the choice of insulator film materials.Type: GrantFiled: November 24, 1999Date of Patent: September 25, 2001Assignee: International Business Machines CorporationInventors: Chung H. Lam, Dale W. Martin, Christa R. Willets
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Patent number: 6180456Abstract: A logic chip including a non-volatile random access memory (NVRAM) array and method of fabrication thereof. The chip includes devices with gates on one or more of three polysilicon layers. Chip logic uses normal FETs and array support includes high voltage FETs. Both logic and support are CMOS. The gates of normal FETs in the chip logic are from the third, uppermost polysilicon layer. The third poly silicon layer also is used as a mask for high voltage FETs and array word lines, both of which use the second polysilicon layer for gates. The first polysilicon layer is used solely for cell floating gates.Type: GrantFiled: February 17, 1999Date of Patent: January 30, 2001Assignee: International Business Machines CorporationInventors: Chung Hon Lam, Glen L. Miles, Jame Spiros Nakos, Christa R. Willets