Patents by Inventor Christelle Rochefort

Christelle Rochefort has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7394144
    Abstract: Consistent with an example embodiment, a reduced surface field effect type (RESURF) semiconductor device is manufactured having a drift region over a drain region. Trenches are formed through openings in mask. A trench insulating layer is deposited on the sidewalls and base of the trenches followed by an overetching step to remove the trench insulating layer from the base of the trenches as well as the top of the sidewalls of the trenches adjacent to the first major surface leaving exposed silicon at the top of the sidewalls of the trench and the base of the trenches. Silicon is selectively grown plugging the trenches with silicon plug (18) leaving void.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: July 1, 2008
    Assignee: NXP B.V.
    Inventors: Christelle Rochefort, Erwin A. Hijzen, Philippe Meunier-Beillard
  • Publication number: 20070228496
    Abstract: A vertical semiconductor device, for example a trench-gate MOSFET power transistor (1), has a drift region (12) of one conductivity type containing spaced vertical columns (30) of the opposite conductivity type for charge compensation increase of the device breakdown voltage. Insulating material (31) is provided on the sidewalls only of trenches (20) in the drift region (12) and the opposite conductivity type material is epitaxially grown from the bottom of the trenches (20). The presence of the sidewall insulating material (31) reduces the possibility of defects during the epitaxial growth and hence excessive leakage currents in the device (1). The insulating material (31) also prevents epitaxial growth on the trench sidewalls and hence substantially prevents forming voids in the trenches which would lessen the accuracy of charge compensation. The epitaxial growth by this method can be well controlled and may be stopped at an upper level (21) below the top major surface (10a).
    Type: Application
    Filed: September 1, 2005
    Publication date: October 4, 2007
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Christelle Rochefort, Erwin Hijzen, Phillippe Meunier-Beillard
  • Publication number: 20070222019
    Abstract: Consistent with an example embodiment, a reduced surface field effect type (RESURF) semiconductor device is manufactured having a drift region over a drain region. Trenches are formed through openings in mask. A trench insulating layer is deposited on the sidewalls and base of the trenches followed by an overetching step to remove the trench insulating layer from the base of the trenches as well as the top of the sidewalls of the trenches adjacent to the first major surface leaving exposed silicon at the top of the sidewalls of the trench and the base of the trenches. Silicon is selectively grown plugging the trenches with silicon plug (18) leaving void.
    Type: Application
    Filed: March 29, 2005
    Publication date: September 27, 2007
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Christelle Rochefort, Erwin Hijzen, Philippe Meunier-Beillard
  • Patent number: 7154177
    Abstract: A semiconductor device has an edge termination region (15) having a plurality of trenches (17). Conductive material (20) and insulating material (19) is formed at the trenches, and surface implants (21) are formed on either side of the trenches. A conductive bridge (23) connects the surface implants (21) to allow equilibrium to be reached in reverse bias.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: December 26, 2006
    Assignee: NXP B.V.
    Inventors: Rob Van Dalen, Christelle Rochefort
  • Publication number: 20050173776
    Abstract: A semiconductor device has an edge termination region (15) having a plurality of trenches (17). Conductive material (20) and insulating material (19) is formed at the trenches, and surface implants (21) are formed on either side of the trenches. A conductive bridge (23) connects the surface implants (21) to allow equilibrium to be reached in reverse bias.
    Type: Application
    Filed: June 13, 2003
    Publication date: August 11, 2005
    Inventors: Rob Dalen, Christelle Rochefort
  • Patent number: 6724021
    Abstract: A semiconductor device, such as a power MOSFET, Schottky rectifier or p-n rectifier, has a voltage-sustaining zone (20) between a first (21, 23, 31a) and second (22) device regions adjacent to respective first and second opposite surfaces (11, 12) of a semiconductor body 10. Trenched field-shaping regions (40) including a resistive path (42) extend through the voltage-sustaining zone (20) to the underlying second region (22), so as to enhance the breakdown voltage of the device. The voltage-sustaining zone (20) and the trenched field-shaping regions (40) are present in both the active device area (A) and in the peripheral area (P) of the device. A further resistive path (53) extends across the first surface (11), outwardly over the peripheral area (P). This further resistive path (53) provides a potential divider that is connected to the respective resistive paths (42) of successive underlying trenched field-shaping regions (40) in the peripheral area (P).
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: April 20, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Rob Van Dalen, Christelle Rochefort, Godefridus A. M. Hurkx
  • Patent number: 6605862
    Abstract: A semiconductor device, such as a MOSFET or PN diode rectifier, has a p-n junction (24) between a first device region (23) and an underlying voltage-sustaining zone (20). Trenched field-shaping regions (40) extend through the voltage-sustaining zone (20) to improve the voltage-blocking and on-resistance characteristics of the device. The trenched field-shaping region (40) comprises a resistive path (42) accommodated in a trench (41) that has an insulating layer (44) at its side-walls. The insulating layer (44) dielectrically couples potential from the resistive path (42) to the voltage-sustaining zone (20) that is depleted in a voltage-blocking mode of operation of the device. The insulating layer (44) extends at the side-walls of the trench (41) to an upper level (81) that is higher than a lower level (82) at which the resistive path (42) starts in the trench (41).
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: August 12, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Rob Van Dalen, Christelle Rochefort, Godefridus A. M. Hurkx
  • Publication number: 20020134998
    Abstract: A semiconductor device, such as a power MOSFET, Schottky rectifier or p-n rectifier, has a voltage-sustaining zone (20) between a first (21, 23, 31a) and second (22) device regions adjacent to respective first and second opposite surfaces (11, 12) of a semiconductor body 10. Trenched field-shaping regions (40) including a resistive path (42) extend through the voltage-sustaining zone (20) to the underlying second region (22), so as to enhance the breakdown voltage of the device. The voltage-sustaining zone (20) and the trenched field-shaping regions (40) are present in both the active device area (A) and in the peripheral area (P) of the device. A further resistive path (53) extends across the first surface (11), outwardly over the peripheral area (P). This further resistive path (53) provides a potential divider that is connected to the respective resistive paths (42) of successive underlying trenched field-shaping regions (40) in the peripheral area (P).
    Type: Application
    Filed: February 4, 2002
    Publication date: September 26, 2002
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Rob Van Dalen, Christelle Rochefort, Godefridus A.M. Hurkx
  • Publication number: 20020130358
    Abstract: A semiconductor device, such as a MOSFET or PN diode rectifier, has a p-n junction (24) between a first device region (23) and an underlying voltage-sustaining zone (20). Trenched field-shaping regions (40) extend through the voltage-sustaining zone (20) to improve the voltage-blocking and on-resistance characteristics of the device. The trenched field-shaping region (40) comprises a resistive path (42) accommodated in a trench (41) that has an insulating layer (44) at its side-walls. The insulating layer (44) dielectrically couples potential from the resistive path (42) to the voltage-sustaining zone (20) that is depleted in a voltage-blocking mode of operation of the device. The insulating layer (44) extends at the side-walls of the trench (41) to an upper level (81) that is higher than a lower level (82) at which the resistive path (42) starts in the trench (41).
    Type: Application
    Filed: February 7, 2002
    Publication date: September 19, 2002
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Rob Van Dalen, Christelle Rochefort, Godefridus A.M. Hurkx