Patents by Inventor Christelle Veytizou

Christelle Veytizou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11688627
    Abstract: A substrate for radiofrequency microelectronic devices comprises a carrier substrate made of a semi-conductor, a sintered composite layer disposed on the carrier substrate and formed from powders of at least a first dielectric material and a second dielectric different from the first material, the sintered composite layer having a thickness larger than 5 microns and a thermal expansion coefficient that is matched with that of the carrier substrate to plus or minus 30%.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 27, 2023
    Assignee: Soitec
    Inventors: Frederic Allibert, Christelle Veytizou, Damien Radisson
  • Publication number: 20220399200
    Abstract: A method for forming a high resistivity handle substrate for a composite substrate comprises: providing a base substrate made of silicon; exposing the base substrate to a carbon single precursor at a pressure below atmospheric pressure to form a polycrystalline silicon carbide layer having a thickness of at least 10 nm on the surface of the base substrate; and then growing a polycrystalline charge trapping layer on the carbon-containing layer.
    Type: Application
    Filed: November 25, 2020
    Publication date: December 15, 2022
    Inventors: Young-Pil Kim, Isabelle Bertrand, Christelle Veytizou
  • Publication number: 20220359272
    Abstract: A semiconductor structure for radio frequency applications includes a support substrate made of silicon and comprising a mesoporous layer, a dielectric layer arranged on the mesoporous layer and a superficial layer arranged on the dielectric layer. The mesoporous layer comprises hollow pores, the internal walls of which are mainly lined with oxide. The mesoporous layer has a thickness between 3 and 40 microns and a resistivity greater than 20 kohm.cm over its entire thickness. The support substrate has a resistivity between 0.5 and 4 ohm.cm. The invention also relates to a method for producing such a semiconductor structure.
    Type: Application
    Filed: March 25, 2020
    Publication date: November 10, 2022
    Inventors: Emmanuel Augendre, Frédéric Gaillard, Thomas Lorne, Emmanuel Rolland, Christelle Veytizou, Isabelle Bertrand, Frédéric Allibert
  • Publication number: 20220301847
    Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 22, 2022
    Inventors: Patrick Reynaud, Marcel Broekaart, Frédéric Allibert, Christelle Veytizou, Luciana Capello, Isabelle Bertrand
  • Patent number: 11373856
    Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 28, 2022
    Assignee: Soitec
    Inventors: Patrick Reynaud, Marcel Broekaart, Frederic Allibert, Christelle Veytizou, Luciana Capello, Isabelle Bertrand
  • Publication number: 20220076991
    Abstract: A semiconductor-on-insulator substrate for radio-frequency applications, comprises: —a silicon carrier substrate, —an electrically insulating layer arranged on the carrier substrate, —a single-crystal layer arranged on the electrically insulating layer, the substrate being characterized in that it further comprises a layer of silicon carbide SiC arranged between the carrier substrate and the electrically insulating layer, which has a thickness between 1 nm and 5 nm, the surface of the layer of silicon carbide SiC that is on the side of the electrically insulating layer being rough.
    Type: Application
    Filed: December 19, 2019
    Publication date: March 10, 2022
    Inventors: Kim Young Pil, Christelle Veytizou
  • Patent number: 11251265
    Abstract: A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: February 15, 2022
    Assignees: Soitec, Centre National de la Recherche Scientifiaue
    Inventors: Christophe Figuet, Oleg Kononchuk, Kassam Alassaad, Gabriel Ferro, Véronique Souliere, Christelle Veytizou, Taguhi Yeghoyan
  • Publication number: 20210183691
    Abstract: A substrate for applications in the fields of radiofrequency electronics and microelectronics, comprises: a base substrate; a single carbon layer positioned on and directly in contact with the base substrate, with the carbon layer having a thickness ranging from 1 nm to 5 nm; an insulator layer positioned on the carbon layer; and a device layer positioned on the insulator layer.
    Type: Application
    Filed: July 5, 2018
    Publication date: June 17, 2021
    Inventors: Christelle Veytizou, Patrick Reynaud, Oleg Kononchuk, Frédéric Allibert
  • Publication number: 20210057635
    Abstract: A hybrid structure for a surface acoustic wave device comprises a working layer of piezoelectric material assembled with a support substrate having a lower coefficient of thermal expansion than that of the working layer, and an intermediate layer located between the working layer and the support substrate. The intermediate layer is a sintered composite layer formed from powders of at least a first material and a second material different from the first.
    Type: Application
    Filed: March 13, 2019
    Publication date: February 25, 2021
    Inventors: Frédéric Allibert, Christelle Veytizou
  • Publication number: 20210028057
    Abstract: A substrate for radiofrequency microelectronic devices comprises a carrier substrate made of a semi-conductor, a sintered composite layer disposed on the carrier substrate and formed from powders of at least a first dielectric material and a second dielectric different from the first material, the sintered composite layer having a thickness larger than 5 microns and a thermal expansion coefficient that is matched with that of the carrier substrate to plus or minus 30%.
    Type: Application
    Filed: March 13, 2019
    Publication date: January 28, 2021
    Inventors: Frederic Allibert, Christelle Veytizou, Damien Radisson
  • Publication number: 20200020520
    Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.
    Type: Application
    Filed: January 11, 2018
    Publication date: January 16, 2020
    Inventors: Patrick Reynaud, Marcel Broekaart, Frederic Allibert, Christelle Veytizou, Luciana Capello, Isabelle Bertrand
  • Publication number: 20190058031
    Abstract: A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.
    Type: Application
    Filed: February 23, 2017
    Publication date: February 21, 2019
    Applicants: Soitec, Centre National de la Recherche Scientifique, Universite Claude Bernard Lyon 1, Soitec
    Inventors: Christophe Figuet, Oleg Kononchuk, Kassam Alassaad, Gabriel Ferro, Véronique Souliere, Christelle Veytizou, Taguhi Yeghoyan
  • Patent number: 9136113
    Abstract: A process for avoiding formation of an Si—SiO2—H2 environment during a dissolution treatment of a semiconductor-on-insulator structure that includes a carrier substrate, an oxide layer, a thin layer of a semiconductor material and a peripheral ring in which the oxide layer is exposed. This process includes encapsulating at least the exposed oxide layer of the peripheral ring with semiconductor material by performing a creep thermal treatment; and performing an oxide dissolution treatment to reduce part of the thickness of the oxide layer. In this process, the semiconductor material that encapsulates the oxide layer has a thickness before the oxide dissolution that is at least twice that of the oxide that is to be dissolved, thus avoiding formation of an Si—SiO2—H2 environment on the peripheral ring where the oxide layer would otherwise be exposed.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: September 15, 2015
    Assignee: SOITEC
    Inventors: Didier Landru, Fabrice Gritti, Eric Guiot, Oleg Kononchuk, Christelle Veytizou
  • Publication number: 20140030877
    Abstract: A process for avoiding formation of a Si—SiO2—H2 environment during a dissolution treatment of a semiconductor-on-insulator structure that includes a carrier substrate, an oxide layer, a thin layer of semiconductor material and a peripheral ring in which the oxide layer is exposed. This process includes encapsulating at least the exposed oxide layer of the peripheral ring with semiconductor material by performing a creep thermal treatment; and performing an oxide dissolution treatment to reduce part of the thickness of the oxide layer. In this process, the semiconductor material that encapsulates the oxide layer has a thickness before the oxide dissolution that is at least twice that of the oxide that is to be dissolved, thus avoiding formation of a Si—SiO2—H2 environment on the peripheral ring where the oxide layer would otherwise be exposed.
    Type: Application
    Filed: October 2, 2013
    Publication date: January 30, 2014
    Applicant: SOITEC
    Inventors: Didier LANDRU, Fabrice GRITTI, Eric GUIOT, Oleg KONONCHUK, Christelle VEYTIZOU
  • Patent number: 8324072
    Abstract: A process for treating a semiconductor-on-insulator type structure that includes, successively, a support substrate, an oxide layer and a thin semiconductor layer. The process includes formation of a silicon nitride or silicon oxynitride mask on the thin semiconductor layer to define exposed areas at the surface of the layer which are not covered by the mask, and which are arranged in a desired pattern; and application of a heat treatment in a neutral or controlled reducing atmosphere and under controlled conditions of temperature and time to induce at least a portion of the oxygen of the oxide layer to diffuse through the thin semiconductor layer, thereby resulting in the controlled reduction in the oxide thickness in the areas of the oxide layer corresponding to the desired pattern. The mask is formed so as to be at least partially buried in the thickness of the thin semiconductor layer.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: December 4, 2012
    Assignee: Soitec
    Inventors: Christelle Veytizou, Fabrice Gritti, Eric Guiot, Oleg Kononchuk, Didier Landru
  • Publication number: 20120199956
    Abstract: The present invention relates to process for recycling a source substrate that has a surface region and regions in relief on the surface region, with the regions in relief corresponding to residual regions of a layer of the source substrate that were not being separated from the rest of the source substrate during a prior removal step. The process includes selective electromagnetic irradiation of the source substrate at a wavelength such that the damaged material of the surface region absorbs the electromagnetic irradiation. The present invention also relates to a recycled source substrate and to a process for transferring a layer from a source substrate recycled for this purpose.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 9, 2012
    Inventors: Monique Lecomte, Pascal Guenard, Sophie Rigal, David Sotta, Fabienne Janin, Christelle Veytizou
  • Publication number: 20120094496
    Abstract: A process for treating a semiconductor-on-insulator type structure that includes, successively, a support substrate, an oxide layer and a thin semiconductor layer. The process includes formation of a silicon nitride or silicon oxynitride mask on the thin semiconductor layer to define exposed areas at the surface of the layer which are not covered by the mask, and which are arranged in a desired pattern; and application of a heat treatment in a neutral or controlled reducing atmosphere and under controlled conditions of temperature and time to induce at least a portion of the oxygen of the oxide layer to diffuse through the thin semiconductor layer, thereby resulting in the controlled reduction in the oxide thickness in the areas of the oxide layer corresponding to the desired pattern. The mask is formed so as to be at least partially buried in the thickness of the thin semiconductor layer.
    Type: Application
    Filed: September 21, 2009
    Publication date: April 19, 2012
    Inventors: Christelle Veytizou, Fabrice Gritti, Eric Guiot, Oleg Kononchuk, Didier Landru
  • Publication number: 20110275226
    Abstract: The invention concerns a process to treat a structure of semiconductor-on-insulator type structure of a carrier substrate, an oxide layer and a thin layer of a semiconductor material, wherein the structure having a peripheral ring in which the oxide layer is exposed, and the process includes the application of a main thermal treatment in a neutral or controlled reducing atmosphere. The method includes a step to cover at least an exposed peripheral part of the oxide layer, prior to the main thermal treatment, this latter treatment being conducted under controlled time and temperature conditions so as to urge at least part of the oxygen in the oxide layer to diffuse through the thin semiconductor layer, leading to controlled reduction of the thickness of the oxide layer.
    Type: Application
    Filed: December 30, 2009
    Publication date: November 10, 2011
    Inventors: Didier Landru, Fabrice Gritti, Eric Guiot, Oleg Kononchuk, Christelle Veytizou
  • Publication number: 20110193201
    Abstract: The present invention notably concerns a method to fabricate and treat a structure of semiconductor-on-insulator type, successively comprising a carrier substrate (1), an oxide layer (3) and a thin layer (2) of semiconducting material, according to which: 1) a mask is formed on said thin layer (2) so as to define exposed regions (20), on the surface of said layer, which are not covered by the mask; 2) heat treatment is applied so as to urge at least part of the oxygen of the oxide layer (3) to diffuse through the thin layer (2), leading to controlled removal of the oxide in the regions (30) of the oxide layer (3) corresponding to the desired pattern; characterized in that said carrier substrate (1) and thin layer (2) are arranged relative to each other so that their crystal lattices, in a plane parallel to their interface (I), together form an angle called a “twist angle” of no more than 1°, and in a plane perpendicular to their interface (I) an angle called a “tilt angle” of no more than 1°, and in that a th
    Type: Application
    Filed: October 9, 2009
    Publication date: August 11, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Oleg Kononchuk, Eric Guiot, Fabrice Gritti, Didier Landru, Christelle Veytizou