Patents by Inventor Christian A. Lutkemeyer
Christian A. Lutkemeyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8601048Abstract: Herein described is a method and system of implementing integrated circuit logic modules that provide maximum efficiency and minimum energy dissipation. In a representative embodiment, a method of implementing one or more digital signal processing functions comprises determining one or more parameters associated with generating an optimal logic module. The one or more parameters may comprise the circuit area of the logic module and the processing time through a critical path of the logic module. In a representative embodiment, the system comprises a logic module that utilizes four full adders arranged in a tree configuration. In a representative embodiment, the logic module comprises a carry-save accumulator that provides maximum efficiency and minimal energy dissipation.Type: GrantFiled: January 5, 2005Date of Patent: December 3, 2013Assignee: Broadcom CorporationInventor: Christian Lutkemeyer
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Patent number: 8422591Abstract: Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation precoding is performed on signals transmitted over an optical channel. In one implementation precoding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.Type: GrantFiled: April 20, 2011Date of Patent: April 16, 2013Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, Gottfried Ungerboeck, Keshab K. Parhi, Christian A. Lutkemeyer, Pieter Vorenkamp, Kevin T. Chan, Myles H. Wakayama
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Publication number: 20110206109Abstract: Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation precoding is performed on signals transmitted over an optical channel. In one implementation precoding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.Type: ApplicationFiled: April 20, 2011Publication date: August 25, 2011Inventors: Oscar E. Agazzi, Gottfried Ungerboeck, Keshab K. Parhi, Christian A. Lutkemeyer, Pieter Vorenkamp, Kevin T. Chan, Myles H. Wakayama
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Patent number: 7933341Abstract: Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation preceding is performed on signals transmitted over an optical channel. In one implementation preceding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.Type: GrantFiled: February 28, 2001Date of Patent: April 26, 2011Inventors: Oscar E. Agazzi, Gottfried Ungerboeck, Keshab K. Parhi, Christian A. Lutkemeyer, Pieter Vorenkamp, Kevin T. Chan, Myles H. Wakayama
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Patent number: 7411523Abstract: Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers Compared to radix-4 Booth coding the proposed method reduces the number of partial products by one, if the input signal has certain limits on its range. One exemplary application is echo cancellation in a full duplex pulse amplitude modulation system with 10 levels (PAM-10). Echo cancellation may be achieved by calculating a digital replica of the echo from the transmission channel. The replica signal may be calculated in a finite impulse response (FIR) filter, which multiplies the transmitted signal with estimates of the echo coefficients of the transmission channel The replica signal may be subtracted from the received signal to create an echo-free receive signal. The disclosed method may reduce the number of partial products between the PAM-10 transmit signal and each echo coefficient from three, when radix-4 Booth coding is used, to two.Type: GrantFiled: May 15, 2007Date of Patent: August 12, 2008Assignee: Broadcom CorporationInventor: Christian Lutkemeyer
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Publication number: 20070210942Abstract: Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers Compared to radix-4 Booth coding the proposed method reduces the number of partial products by one, if the input signal has certain limits on its range. One exemplary application is echo cancellation in a full duplex pulse amplitude modulation system with 10 levels (PAM-10). Echo cancellation may be achieved by calculating a digital replica of the echo from the transmission channel. The replica signal may be calculated in a finite impulse response (FIR) filter, which multiplies the transmitted signal with estimates of the echo coefficients of the transmission channel The replica signal may be subtracted from the received signal to create an echo-free receive signal. The disclosed method may reduce the number of partial products between the PAM-10 transmit signal and each echo coefficient from three, when radix-4 Booth coding is used, to two.Type: ApplicationFiled: May 15, 2007Publication date: September 13, 2007Inventor: Christian Lutkemeyer
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Publication number: 20070189376Abstract: A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.Type: ApplicationFiled: February 13, 2007Publication date: August 16, 2007Inventors: Arthur Abnous, Avanindra Madisetti, Christian Lutkemeyer
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Patent number: 7218253Abstract: Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers. Compared to radix-4 Booth coding the proposed method reduces the number of partial products by one, if the input signal has certain limits on its range. One exemplary application is echo cancellation in a full duplex pulse amplitude modulation system with 10 levels (PAM-10). Echo cancellation may be achieved by calculating a digital replica of the echo from the transmission channel. The replica signal may be calculated in a finite impulse response (FIR) filter, which multiplies the transmitted signal with estimates of the echo coefficients of the transmission channel. The replica signal may be subtracted from the received signal to create an echo-free receive signal. The disclosed method may reduce the number of partial products between the PAM-10 transmit signal and each echo coefficient from three, when radix-4 Booth coding is used, to two.Type: GrantFiled: February 15, 2005Date of Patent: May 15, 2007Assignee: Broadcom CorporationInventor: Christian Lutkemeyer
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Patent number: 7218156Abstract: A circuit for and method of operating a supply tracking clock multiplier is provided. An embodiment of the present invention may permit a less power consuming portion of an integrated circuit to operate at a relatively higher average clock rate than a more power consuming portion operating at a relatively lower clock rate, by adjusting the duration of the cycles of the higher frequency clock. The adjustment may be according to the supply voltage changes that result from logic switching activity of the more power consuming portion, and may be performed in a manner that substantially matches the delay behavior of the logic. The phase of the higher frequency clock remains locked to the lower frequency clock. An embodiment of the present invention may reduce the area and cost of an integrated circuit by minimizing the need for other on-chip power supply noise mitigation approaches, while also improving device throughput and performance.Type: GrantFiled: October 11, 2006Date of Patent: May 15, 2007Assignee: Broadcom CorporationInventor: Christian Lütkemeyer
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Publication number: 20070094318Abstract: Certain aspects of a method and system for implementing approximation of a square function may comprise generating an output value by subtracting an absolute value of a first received input and a second received input. The generated output may be left shifted so as to generate a left shifted value. An output may be generated by left shifting by a plurality of bits, a sum of the generated left shifted value and the absolute value of the first received input. The second received input S may be determined by S=2?log2X?, where X is the first received input. The plurality of bits used for left shifting during generation of the output may be determined by log2(S). A leading ‘1’ in the first received input may be detected in order to generate the second received input.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventor: Christian Lutkemeyer
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Patent number: 7177894Abstract: A system and method for reducing power consumption in digital circuitry by reducing the amount of unnecessary switching in such circuitry. An aspect of the present invention provides a switching-reduction circuit that outputs a signal to a subsequent digital circuit. The value of the signal may depend on the relevance of the signal value to a next output of the subsequent digital circuit. A method according to various aspects of the present invention includes receiving a next input signal. The method further includes determining whether the next input signal may be relevant to a next output of a subsequent digital circuit. The method further includes providing the next input signal to the subsequent digital circuit when the next input signal may be relevant to the next output of the subsequent digital circuit, and providing a previous signal to the subsequent digital circuit when the next input signal will not be relevant to the next output of the subsequent digital circuit.Type: GrantFiled: August 28, 2003Date of Patent: February 13, 2007Assignee: Broadcom CorporationInventor: Christian Lutkemeyer
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Publication number: 20070030044Abstract: A circuit for and method of operating a supply tracking clock multiplier is provided. An embodiment of the present invention may permit a less power consuming portion of an integrated circuit to operate at a relatively higher average clock rate than a more power consuming portion operating at a relatively lower clock rate, by adjusting the duration of the cycles of the higher frequency clock. The adjustment may be according to the supply voltage changes that result from logic switching activity of the more power consuming portion, and may be performed in a manner that substantially matches the delay behavior of the logic. The phase of the higher frequency clock remains locked to the lower frequency clock. An embodiment of the present invention may reduce the area and cost of an integrated circuit by minimizing the need for other on-chip power supply noise mitigation approaches, while also improving device throughput and performance.Type: ApplicationFiled: October 11, 2006Publication date: February 8, 2007Inventor: Christian Lutkemeyer
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Patent number: 7123063Abstract: A circuit for and method of operating a supply tracking clock multiplier is provided. An embodiment of the present invention may permit a less power consuming portion of an integrated circuit to operate at a relatively higher average clock rate than a more power consuming portion operating at a relatively lower clock rate, by adjusting the duration of the cycles of the higher frequency clock. The adjustment may be according to the supply voltage changes that result from logic switching activity of the more power consuming portion, and may be performed in a manner that substantially matches the delay behavior of the logic. The phase of the higher frequency clock remains locked to the lower frequency clock. An embodiment of the present invention may reduce the area and cost of an integrated circuit by minimizing the need for other on-chip power supply noise mitigation approaches, while also improving device throughput and performance.Type: GrantFiled: April 28, 2004Date of Patent: October 17, 2006Assignee: Broadcom CorporationInventor: Christian Lütkemeyer
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Publication number: 20060149805Abstract: Herein described is a method and system of implementing integrated circuit logic modules that provide maximum efficiency and minimum energy dissipation. In a representative embodiment, a method of implementing one or more digital signal processing functions comprises determining one or more parameters associated with generating an optimal logic module. The one or more parameters may comprise the circuit area of the logic module and the processing time through a critical path of the logic module. In a representative embodiment, the system comprises a logic module that utilizes four full adders arranged in a tree configuration. In a representative embodiment, the logic module comprises a carry-save accumulator that provides maximum efficiency and minimal energy dissipation.Type: ApplicationFiled: January 5, 2005Publication date: July 6, 2006Inventor: Christian Lutkemeyer
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Publication number: 20050242868Abstract: A circuit for and method of operating a supply tracking clock multiplier is provided. An embodiment of the present invention may permit a less power consuming portion of an integrated circuit to operate at a relatively higher average clock rate than a more power consuming portion operating at a relatively lower clock rate, by adjusting the duration of the cycles of the higher frequency clock. The adjustment may be according to the supply voltage changes that result from logic switching activity of the more power consuming portion, and may be performed in a manner that substantially matches the delay behavior of the logic. The phase of the higher frequency clock remains locked to the lower frequency clock. An embodiment of the present invention may reduce the area and cost of an integrated circuit by minimizing the need for other on-chip power supply noise mitigation approaches, while also improving device throughput and performance.Type: ApplicationFiled: April 28, 2004Publication date: November 3, 2005Inventor: Christian Lutkemeyer
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Publication number: 20050175087Abstract: Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers. Compared to radix-4 Booth coding the proposed method reduces the number of partial products by one, if the input signal has certain limits on its range. One exemplary application is echo cancellation in a full duplex pulse amplitude modulation system with 10 levels (PAM-10). Echo cancellation may be achieved by calculating a digital replica of the echo from the transmission channel. The replica signal may be calculated in a finite impulse response (FIR) filter, which multiplies the transmitted signal with estimates of the echo coefficients of the transmission channel. The replica signal may be subtracted from the received signal to create an echo-free receive signal. The disclosed method may reduce the number of partial products between the PAM-10 transmit signal and each echo coefficient from three, when radix-4 Booth coding is used, to two.Type: ApplicationFiled: February 15, 2005Publication date: August 11, 2005Inventor: Christian Lutkemeyer
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Patent number: 6864812Abstract: Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers. Compared to radix-4 Booth coding the proposed method reduces the number of partial products by one, if the input signal has certain limits on its range. One exemplary application is echo cancellation in a fill duplex pulse amplitude modulation system with 10 levels (PAM-10). Echo cancellation may be achieved by calculating a digital replica of the echo from the transmission channel. The replica signal may be calculated in a finite impulse response (FIR) filter, which multiplies the transmitted signal with estimates of the echo coefficients of the transmission channel. The replica signal may be subtracted from the received signal to create an echo-free receive signal. The disclosed method may reduce the number of partial products between the PAM-10 transmit signal and each echo coefficient from three, when radix-4 Booth coding is used, to two.Type: GrantFiled: February 5, 2004Date of Patent: March 8, 2005Assignee: Broadcom CorporationInventor: Christian Lutkemeyer
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Publication number: 20050050133Abstract: A system and method for reducing power consumption in digital circuitry by reducing the amount of unnecessary switching in such circuitry. An aspect of the present invention provides a switching-reduction circuit that outputs a signal to a subsequent digital circuit. The value of the signal may depend on the relevance of the signal value to a next output of the subsequent digital circuit. A method according to various aspects of the present invention includes receiving a next input signal. The method further includes determining whether the next input signal may be relevant to a next output of a subsequent digital circuit. The method further includes providing the next input signal to the subsequent digital circuit when the next input signal may be relevant to the next output of the subsequent digital circuit, and providing a previous signal to the subsequent digital circuit when the next input signal will not be relevant to the next output of the subsequent digital circuit.Type: ApplicationFiled: August 28, 2003Publication date: March 3, 2005Inventor: Christian Lutkemeyer
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Publication number: 20010035994Abstract: Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation preceding is performed on signals transmitted over an optical channel. In one implementation preceding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.Type: ApplicationFiled: February 28, 2001Publication date: November 1, 2001Inventors: Oscar E. Agazzi, Gottfried Ungerboeck, Keshab K. Parhi, Christian A. Lutkemeyer, Pieter Vorenkamp, Kevin T. Chan, Myles H. Wakayama