Abstract: A method of forming planar isolation regions in semiconductor structures includes providing a semiconductor substrate and forming a semiconductor layer thereon. A dielectric layer comprising at least two different dielectric materials is disposed on the semiconductor layer and a trench is etched therethrough and into the semiconductor layer. Dielectric sidewalls are formed in the trench which is then filled by selectively forming depositing polycrystalline silicon therein. The semiconductor material is then at least partially oxidized to form the planar isolation region. The isolation regions disclosed herein may be used for both intradevice and interdevice isolation.

Abstract: A method for selectively depositing amorphous or polycrystalline silicon wherein a wafer having exposed silicon regions thereon is placed into a CVD reactor and subjected to a silicon containing gas and a halogen containing gas, at least one of which flows into the reactor with a hydrogen carrier gas. Amorphous silicon may be selectively deposited in the range of approximately 200 to 550 degrees centigrade while polycrystalline silicon may be selectively deposited in the range of approximately 550 to 750 degrees centigrade. It is also possible to deposit polycrystalline silicon at temperatures in the range of approximately 750 to 1000 degrees centigrade by employing another embodiment of the present invention.

Abstract: The process utilizes a volatile organo halosilane, such as trimethylchlorosilane, injected through a mass flow controller into a deposition, or like, reactor to dry the mass flow controller, transfer lines and injectors, the deposition surfaces and reactor walls, the exhaust manifold, and vacuum pump and oil.

Abstract: A process and apparatus for LPCVD of thin metallic films is disclosed. The apparatus includes a U-shaped injection tube through which high molecular weight reactants are injected into a reaction chamber. The input and output ends of the U-shaped tube are coupled to a removeable feedthrough plate which, in turn, is coupled to the end cap which seals one end of the reaction chamber. A deposition surface is placed in the chamber through a second end cap at the opposite end of the chamber. The output end of the U-shaped injection tube is coupled to a vacuum pump and the high molecular weight reactant is drawn through the injection tube and dispersed in the reaction chamber through a plurality of holes in the input side of the injection tube.

Abstract: An MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to improve oxidation protection.

Abstract: An MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to improve oxidation protection.

Abstract: A bidirectional line driver circuit for transmitting logic signals on a highly capacitive, or low impedance transmission line makes use of a tandem connection of switching means for providing a low impedance connection from the output of the driver circuit to either a first power supply voltage or a second power supply voltage to define transmitted logic levels. Coupled to the tandem switching means is a buffered feedback circuit which responds to conduction of the first switching means connected to the first power supply voltage such that nonconduction is produced in the second switching means connected to the second power supply voltage. A buffer transistor is incorporated in the feedback circuit to insure that this response occurs without significant loading of the output terminal thus eliminating the possibility of oscillation and providing for very high speed switching performance.