Abstract: Disclosed is a memory cell including parallel-connected first access transistors and a first variable resistor in series between a bitline and a source line and parallel-connected second access transistors and a second variable resistor in series between the bitline and the source line. A write wordline controls one pair of first and second access transistors so that, during an initialization mode, the resistors are concurrently subjected to the same write bias conditions for one-time programming to switch from an unprogrammed state (where the resistors have the same first resistance state) to a programmed state (where one resistor has switched to a second resistance state and a bit is stored). Discrete first and second read wordlines control another pair of first and second access transistors to enable discrete read processes associated with the first and second variable resistors. Also disclosed are an associated circuit (e.g., a PUF) and a method.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a soluble self-aligned barrier first for interconnect structure and methods of manufacture. The structure includes: a self-aligning barrier layer lining a trench of an interconnect structure; and an alloy interconnect material over the self-aligned barrier layer. The alloy interconnect material is an alloy composed of metal interconnect material and pre-anneal material that also forms the self-aligning barrier layer.

Abstract: The disclosure relates to integrated circuit (IC) fabrication techniques. Methods according to the disclosure can include: forming a reaction layer on the upper surface of a conductor, the upper surface of a refractory metal liner, and the upper surface of an insulator layer; annealing the reaction layer such that a portion of the reaction layer reacts with the conductor to form a semiconductor-metal alloy region; removing a portion of the reaction layer to expose the refractory metal liner; removing a portion of the refractory metal liner to approximately a depth of the semiconductor-metal alloy region; and removing the semiconductor-metal alloy region to expose a portion of the conductor such that a remainder of the conductor and a remainder of the refractory metal liner are recessed relative to an upper surface of the insulator layer.

Abstract: The disclosure relates to integrated circuit (IC) fabrication techniques. Methods according to the disclosure can include: forming a reaction layer on the upper surface of a conductor, the upper surface of a refractory metal liner, and the upper surface of an insulator layer; annealing the reaction layer such that a portion of the reaction layer reacts with the conductor to form a semiconductor-metal alloy region; removing a portion of the reaction layer to expose the refractory metal liner; removing a portion of the refractory metal liner to approximately a depth of the semiconductor-metal alloy region; and removing the semiconductor-metal alloy region to expose a portion of the conductor such that a remainder of the conductor and a remainder of the refractory metal liner are recessed relative to an upper surface of the insulator layer.

Abstract: A Cu interconnect is formed with improved directionality and smoothness. Embodiments include wet etching Cu while applying a pulsing electric current. An embodiment includes forming a Cu layer, and patterning the Cu layer by exposing it to a wet etching solution which includes a passivating surface active agent while simultaneously applying an electric current. The etching solution may be a mild acid. A UV light may be applied simultaneously with the electric current. The electric current may be pulsed with a cycle frequency between 50 kHz and 500 kHz.

Abstract: Methods for forming copper interconnects for semiconductor devices are provided. In an exemplary embodiment, a method for forming a copper interconnect comprises depositing copper into a trench formed in a dielectric material overlying a semiconductor material. A force is applied to the semiconductor material and stress is induced within the copper deposited in the trench. Recrystallization and grain growth are effected within the copper and the stress is removed.

Abstract: Methods for forming copper interconnects for semiconductor devices are provided. In an exemplary embodiment, a method for forming a copper interconnect comprises depositing copper into a trench formed in a dielectric material overlying a semiconductor material. A force is applied to the semiconductor material and stress is induced within the copper deposited in the trench. Recrystallization and grain growth are effected within the copper and the stress is removed.