Patents by Inventor Christian AMSINCK

Christian AMSINCK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10043234
    Abstract: A system and method for decompressing compressed data (e.g., in a frame buffer) and optionally recompressing the data. The method includes determining a portion of an image to be accessed from a memory and sending a conditional read corresponding to the portion of the image. In response to the conditional read, an indicator operable to indicate that the portion of the image is uncompressed may be received. If the portion of the image is compressed, in response to the conditional read, compressed data corresponding to the portion of the image is received. In response to receiving the compressed data, the compressed data is uncompressed into uncompressed data. The uncompressed data may then be written to the memory corresponding to the portion of the image. The uncompressed data may then be in-place compressed for or during subsequent processing.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: August 7, 2018
    Assignee: NVIDIA Corporation
    Inventors: Jonathan Dunaisky, Steven E. Molnar, Christian Amsinck, Rui Bastos, Eric B. Lum, Justin Cobb, Emmett Kilgariff
  • Patent number: 10008029
    Abstract: Updating depth related graphics data is described. Geometric primitives are processed. Pixels are generated from the primitives based on the processing, each of which has at least one corresponding depth value. Culling is performed on a first group of the pixels, based on a representation of the at least one depth related value corresponding to each. Pixels may be discarded based on the culling and upon which a second group of pixels remain. A depth related raster operations function is performed, in which data is transacted with a depth buffer. The culling function is updated in relation to the transacting. The updating is performed on the basis of a granularity, which characterizes the culling function.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: June 26, 2018
    Assignee: Nvidia Corporation
    Inventors: Christian Amsinck, Eric B. Lum, Barry Rodgers, Tony Louca, Christian Rouet, Jonathan Dunaisky
  • Patent number: 9916680
    Abstract: Techniques are disclosed for suppressing access to a depth processing unit associated with a graphics processing pipeline. The method includes receiving a graphics primitive from a first pipeline stage associated with the graphics processing pipeline. The method further includes determining that the graphics primitive is visible over one or more graphics primitives previously rendered to a frame buffer, and determining that the depth buffer is in a read-only mode. The method further includes suppressing an operation to transmit the graphics primitive to the depth processing unit. One advantage of the disclosed technique is that power consumption is reduced within the GPU by avoiding unnecessary accesses to the depth processing unit.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: March 13, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Christian Amsinck, Christian Rouet, Tony Louca
  • Patent number: 9754561
    Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: September 5, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Jonathan Dunaisky, Henry Packard Moreton, Jeffrey A. Bolz, Yury Y. Uralsky, James Leroy Deming, Rui M. Bastos, Patrick R. Brown, Amanpreet Grewal, Christian Amsinck, Poornachandra Rao, Jerome F. Duluk, Jr., Andrew J. Tao
  • Patent number: 9697641
    Abstract: One embodiment of the present invention sets forth a technique for converting alpha values into pixel coverage masks. Geometric coverage is sampled at a number of “real” sample positions within each pixel. Color and depth values are computed for each of these real samples. Fragment alpha values are used to determine an alpha coverage mask for the real samples and additional “virtual” samples, in which the number of bits set in the mask bits is proportional to the alpha value. An alpha-to-coverage mode uses the virtual samples to increase the number of transparency levels for each pixel compared with using only real samples. The alpha-to-coverage mode may be used in conjunction with virtual coverage anti-aliasing to provide higher-quality transparency for rendering anti-aliased images.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: July 4, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Steven E. Molnar, Emmett M. Kilgariff, Walter E. Donovan, Christian Amsinck, Robert Ohannessian
  • Patent number: 9390464
    Abstract: A raster operations (ROP) unit is configured to compress stencil values included in a stencil buffer. The ROP unit divides the stencil values into groups, subdivides each group into two halves, and selects an anchor value for each half. If the difference between each of the stencil values and the corresponding anchor lies within an offset range, and the difference between the two anchors lies within a delta range, then the group is compressible. For a compressible group, the ROP unit encodes the anchor value, offsets from anchors, and an anchor delta. This encoding enables the ROP unit to operate on the compressed group instead of the uncompressed stencil values, reducing the number of memory and computational operations associated with the stencil values. Consequently, the ROP unit reduces memory bandwidth use, reduces power consumption, and increases rendering rate compared to conventional ROP units that implement less flexible compression techniques.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: July 12, 2016
    Assignee: NVIDIA Corporation
    Inventors: Christian Amsinck, Bengt-olaf Schneider, Jeffrey A. Bolz
  • Patent number: 9183609
    Abstract: A technique for efficiently rendering content reduces each complex blend mode to a series of basic blend operations. The series of basic blend operations are executed within a recirculating pipeline until a final blended value is computed. The recirculating pipeline is positioned within a color raster operations unit of a graphics processing unit for efficient access to image buffer data.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 10, 2015
    Assignee: NVIDIA Corporation
    Inventors: Rui Bastos, Mark J. Kilgard, William Craig McKnight, Jerome F. Duluk, Jr., Pierre Souillot, Dale L. Kirkland, Christian Amsinck, Joseph Detmer, Christian Rouet, Don Bittel
  • Publication number: 20150154733
    Abstract: A raster operations (ROP) unit is configured to compress stencil values included in a stencil buffer. The ROP unit divides the stencil values into groups, subdivides each group into two halves, and selects an anchor value for each half. If the difference between each of the stencil values and the corresponding anchor lies within an offset range, and the difference between the two anchors lies within a delta range, then the group is compressible. For a compressible group, the ROP unit encodes the anchor value, offsets from anchors, and an anchor delta. This encoding enables the ROP unit to operate on the compressed group instead of the uncompressed stencil values, reducing the number of memory and computational operations associated with the stencil values. Consequently, the ROP unit reduces memory bandwidth use, reduces power consumption, and increases rendering rate compared to conventional ROP units that implement less flexible compression techniques.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 4, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Christian AMSINCK, Bengt-olaf SCHNEIDER, Jeffrey A. BOLZ
  • Publication number: 20150097847
    Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Jonathan DUNAISKY, Henry Packard MORETON, Jeffrey A. BOLZ, Yury Y. URALSKY, James Leroy DEMING, Rui M. BASTOS, Patrick R. BROWN, Amanpreet GREWAL, Christian AMSINCK, Poornachandra RAO, Jerome F. DULUK, JR., Andrew J. TAO
  • Patent number: 9002125
    Abstract: A method for compressing graphics data comprises selecting z-planes from a plurality of z-planes. The selected z-planes are predictor z-planes. A residual is determined for each sample not covered by one of the predictor z-planes. A sample is covered by one of the predictor z-planes when the predictor z-plane correctly defines a z-value of the sample. A residual comprises a value that is a difference between a predicted z-value provided by one of the predictor z-planes and an actual z-value for the sample. The predictor z-planes and the residuals are stored in a z-buffer.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: April 7, 2015
    Assignee: NVIDIA Corporation
    Inventors: Bengt-Olaf Schneider, Christian Amsinck
  • Publication number: 20140354634
    Abstract: Updating depth related graphics data is described. Geometric primitives are processed. Pixels are generated from the primitives based on the processing, each of which has at least one corresponding depth value. Culling is performed on a first group of the pixels, based on a representation of the at least one depth related value corresponding to each. Pixels may be discarded based on the culling and upon which a second group of pixels remain. A depth related raster operations function is performed, in which data is transacted with a depth buffer. The culling function is updated in relation to the transacting. The updating is performed on the basis of a granularity, which characterizes the culling function.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Inventors: Christian AMSINCK, Eric B. LUM, Barry RODGERS, Tony LOUCA, Christian ROUET, Jonathan DUNAISKY
  • Publication number: 20140184601
    Abstract: A system and method for decompressing compressed data (e.g., in a frame buffer) and optionally recompressing the data. The method includes determining a portion of an image to be accessed from a memory and sending a conditional read corresponding to the portion of the image. In response to the conditional read, an indicator operable to indicate that the portion of the image is uncompressed may be received. If the portion of the image is compressed, in response to the conditional read, compressed data corresponding to the portion of the image is received. In response to receiving the compressed data, the compressed data is uncompressed into uncompressed data. The uncompressed data may then be written to the memory corresponding to the portion of the image. The uncompressed data may then be in-place compressed for or during subsequent processing.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: NVIDIA Corporation
    Inventors: Jonathan Dunaisky, Steven E. Molnar, Christian Amsinck, Rui Bastos, Eric B. Lum, Justin Cobb, Emmett Kilgariff
  • Publication number: 20140176568
    Abstract: A technique for efficiently rendering content reduces each complex blend mode to a series of basic blend operations. The series of basic blend operations are executed within a recirculating pipeline until a final blended value is computed. The recirculating pipeline is positioned within a color raster operations unit of a graphics processing unit for efficient access to image buffer data.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Rui BASTOS, Mark J. Kilgard, William Craig McKnight, Jerome F. Duluk, Pierre Souillot, Dale L. Kirkland, Christian Amsinck, Joseph Detmer, Christian Rouet, Don Bittel
  • Publication number: 20140105513
    Abstract: A method for compressing graphics data comprises selecting z-planes from a plurality of z-planes. The selected z-planes are predictor z-planes. A residual is determined for each sample not covered by one of the predictor z-planes. A sample is covered by one of the predictor z-planes when the predictor z-plane correctly defines a z-value of the sample. A residual comprises a value that is a difference between a predicted z-value provided by one of the predictor z-planes and an actual z-value for the sample. The predictor z-planes and the residuals are stored in a z-buffer.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Bengt-Olaf Schneider, Christian Amsinck
  • Publication number: 20140104267
    Abstract: Techniques are disclosed for suppressing access to a depth processing unit associated with a graphics processing pipeline. The method includes receiving a graphics primitive from a first pipeline stage associated with the graphics processing pipeline. The method further includes determining that the graphics primitive is visible over one or more graphics primitives previously rendered to a frame buffer, and determining that the depth buffer is in a read-only mode. The method further includes suppressing an operation to transmit the graphics primitive to the depth processing unit. One advantage of the disclosed technique is that power consumption is reduced within the GPU by avoiding unnecessary accesses to the depth processing unit.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Christian AMSINCK, Christian ROUET, Tony LOUCA
  • Patent number: 8669999
    Abstract: One embodiment of the present invention sets forth a technique for converting alpha values into pixel coverage masks. Geometric coverage is sampled at a number of “real” sample positions within each pixel. Color and depth values are computed for each of these real samples. Fragment alpha values are used to determine an alpha coverage mask for the real samples and additional “virtual” samples, in which the number of bits set in the mask bits is proportional to the alpha value. An alpha-to-coverage mode uses the virtual samples to increase the number of transparency levels for each pixel compared with using only real samples. The alpha-to-coverage mode may be used in conjunction with virtual coverage anti-aliasing to provide higher-quality transparency for rendering anti-aliased images.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 11, 2014
    Assignee: NVIDIA Corporation
    Inventors: Walter E. Donovan, Emmett M. Kilgariff, Steven E. Molnar, Christian Amsinck, Robert Ohannessian
  • Publication number: 20110090250
    Abstract: One embodiment of the present invention sets forth a technique for converting alpha values into pixel coverage masks. Geometric coverage is sampled at a number of “real” sample positions within each pixel. Color and depth values are computed for each of these real samples. Fragment alpha values are used to determine an alpha coverage mask for the real samples and additional “virtual” samples, in which the number of bits set in the mask bits is proportional to the alpha value. An alpha-to-coverage mode uses the virtual samples to increase the number of transparency levels for each pixel compared with using only real samples. The alpha-to-coverage mode may be used in conjunction with virtual coverage anti-aliasing to provide higher-quality transparency for rendering anti-aliased images.
    Type: Application
    Filed: October 14, 2010
    Publication date: April 21, 2011
    Inventors: Steven E. MOLNAR, Emmett M. KILGARIFF, Walter E. DONOVAN, Christian AMSINCK, Robert OHANNESSIAN
  • Publication number: 20110090251
    Abstract: One embodiment of the present invention sets forth a technique for converting alpha values into pixel coverage masks. Geometric coverage is sampled at a number of “real” sample positions within each pixel. Color and depth values are computed for each of these real samples. Fragment alpha values are used to determine an alpha coverage mask for the real samples and additional “virtual” samples, in which the number of bits set in the mask bits is proportional to the alpha value. An alpha-to-coverage mode uses the virtual samples to increase the number of transparency levels for each pixel compared with using only real samples. The alpha-to-coverage mode may be used in conjunction with virtual coverage anti-aliasing to provide higher-quality transparency for rendering anti-aliased images.
    Type: Application
    Filed: October 14, 2010
    Publication date: April 21, 2011
    Inventors: Walter E. Donovan, Emmett M. Kilgariff, Steven E. Molnar, Christian Amsinck, Robert Ohannessian