Abstract: A conductor terminal, including a spring-force clamping connection for clamping an electrical conductor via spring force. The spring-force clamping connection having a clamping spring, which includes a clamping leg for clamping the electrical conductor on a clamping surface, a spring bend, and a contact leg for fastening and supporting the clamping spring against a clamping force applied by the clamping leg to the electrical conductor. The clamping leg being connected to the contact leg via the spring bend, and the contact leg being fixed to a holder. An actuating area deflects the clamping leg by manually actuating the actuating area. The clamping leg extending from the spring bend to a free end of the clamping spring in a longitudinal direction, and the actuating area being arranged eccentrically to the clamping leg in a width direction of the clamping leg which is orthogonal to the longitudinal direction.

Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.

Abstract: A circuit arrangement includes a semiconductor switch having a control terminal and a load path. A drive circuit is coupled to the control terminal of the semiconductor switch. The drive circuit has a current measuring arrangement for determining a load current flowing through the load path and is designed to prevent the semiconductor switch from being driven in the off state if the load current exceeds a predetermined load current threshold value. A fuse is coupled in series with the load path of the semiconductor switch triggers if a triggering condition dependent at least on the load current is present.

Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.

Abstract: The present invention relates to a circuit arrangement having the following features: a load transistor having a control connection and a first and second load connection; a drive connection coupled to the control connection of the load transistor and serving for the application of a drive signal; a voltage limiting circuit connected between one of the load connections and the drive connection of the transistor; and a deactivation circuit connected to the voltage limiting circuit and serving for the deactivation of the voltage limiting circuit in a manner dependent on a deactivation signal, which is dependent on a load current through the load transistor and/or on a drive voltage of the load transistor.

Abstract: A vehicle on-board electric power system is disclosed including at least one field-effect-controlled power transistor which applies a vehicle on-board electric power system supply voltage VBB to a load when actuated by a logic circuit. The power transistor has a drain-source breakdown voltage VDS with a positive temperature coefficient TKDS and is provided with a clamping means for protecting against overvoltages VO occurring in the vehicle on-board electric power system. The clamping means has a clamping voltage VCLAMP with a positive temperature coefficient TKCLAMP?TKDS, the clamping voltage VCLAMP being lower than or equal to an anticipated maximum overvoltage VOmax in the vehicle on-board electric power system.

Abstract: The present invention relates to a circuit arrangement having the following features: a load transistor having a control connection and a first and second load connection, a drive connection coupled to the control connection of the load transistor and serving for the application of a drive signal, a voltage limiting circuit connected between one of the load connections and the drive connection of the transistor, a deactivation circuit connected to the voltage limiting circuit and serving for the deactivation of the voltage limiting circuit in a manner dependent on a deactivation signal, which is dependent on a load current through the load transistor and/or on a drive voltage of the load transistor.

Abstract: The measurement of a current through a load transistor is described.

Abstract: A protection circuit includes an interruption device formed to interrupt a current path between a protection circuit input and a protection circuit output upon exceeding a predetermined temperature at a temperature measurement location, and a control device formed to generate a control signal depending on a current in the current path, wherein the protection circuit is formed to increase the temperature at the temperature measurement location or decrease the predetermined temperature, when the control signal indicates that the current in the current path is higher than a threshold value current.

Abstract: The measurement of a current through a load transistor is described.

Abstract: A circuit arrangement includes a semiconductor switch having a control terminal and a load path. A drive circuit is coupled to the control terminal of the semiconductor switch. The drive circuit has a current measuring arrangement for determining a load current flowing through the load path and is designed to prevent the semiconductor switch from being driven in the off state if the load current exceeds a predetermined load current threshold value. A fuse is coupled in series with the load path of the semiconductor switch triggers if a triggering condition dependent at least on the load current is present.

Abstract: An apparatus for generating a power signal from a load current is described, has a controller with a load current input, a load current output, an intermediate signal output, and a status signal output, an influencing device with an intermediate signal input and a power signal output, and an interruption device with an interrupt input, an interrupt output, and a status signal input. The controller generates a status signal and an intermediate signal depending on the load current, and the interruption device interrupts the power signal if the status signal satisfies a predetermined first condition, and otherwise lets the power signal pass, and the influencing device generates the intermediate signal as the power signal and output the same at the power signal output if the intermediate signal does not satisfy a predetermined second condition, and otherwise generates and output a power signal with a predetermined value.

Abstract: A vehicle on-board electric power system is disclosed including at least one field-effect-controlled power transistor which applies a vehicle on-board electric power system supply voltage VBB to a load when actuated by a logic circuit. The power transistor has a drain-source breakdown voltage VDS with a positive temperature coefficient TKDS and is provided with a clamping means for protecting against overvoltages VO occurring in the vehicle on-board electric power system. The clamping means has a clamping voltage VCLAMP with a positive temperature coefficient TKCLAMP?TKDS, the clamping voltage VCLAMP being lower than or equal to an anticipated maximum overvoltage VOmax in the vehicle on-board electric power system.

Abstract: An apparatus for generating a power signal from a load current is described, has a controller with a load current input, a load current output, an intermediate signal output, and a status signal output, an influencing device with an intermediate signal input and a power signal output, and an interruption device with an interrupt input, an interrupt output, and a status signal input. The controller generates a status signal and an intermediate signal depending on the load current, and the interruption device interrupts the power signal if the status signal satisfies a predetermined first condition, and otherwise lets the power signal pass, and the influencing device generates the intermediate signal as the power signal and output the same at the power signal output if the intermediate signal does not satisfy a predetermined second condition, and otherwise generates and output a power signal with a predetermined value.

Abstract: A protection circuit includes an interruption device formed to interrupt a current path between a protection circuit input and a protection circuit output upon exceeding a predetermined temperature at a temperature measurement location, and a control device formed to generate a control signal depending on a current in the current path, wherein the protection circuit is formed to increase the temperature at the temperature measurement location or decrease the predetermined temperature, when the control signal indicates that the current in the current path is higher than a threshold value current.

Abstract: Circuit arrangement having a load transistor and a voltage limiting circuit and method for driving a load transistor The present invention relates to a circuit arrangement having the following features: a load transistor (T) having a control connection (G) and a first and second load connection (D, S), a drive connection (IN) coupled to the control connection (G) of the load transistor (T) and serving for the application of a drive signal (Sin), a voltage limiting circuit (10) connected between one (D) of the load connections and the drive connection (G) of the transistor, a deactivation circuit (20) connected to the voltage limiting circuit (10) and serving for the deactivation of the voltage limiting circuit (10) in a manner dependent on a deactivation signal (S22; S23), which is dependent on a load current (Id) through the load transistor (T) and/or on a drive voltage (Vgs) of the load transistor (T). The invention furthermore relates to a method for driving a load transistor.

Abstract: An acoustic signal generator, and a method for generating an acoustic signal are described. The acoustic signal generator has a membrane that can oscillate, a deflection sensor for detecting any deflection of the membrane, an exciter configuration that is coupled to the membrane, and a power semiconductor switch with a load path that is connected to the exciter configuration. The switch has a drive connection. A drive circuit has a first connection connected to the drive connection of the power semiconductor switch and at which a drive signal is available. The drive circuit further has a second connection, to which the deflection sensor is connected.

Abstract: A method for forming interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A encapsulating dielectric layer is formed over the array of MTJ stacks and the lower metallization level. Then, a via opening is defined in the encapsulating dielectric layer, and a planar interlevel dielectric (ILD) layer is deposited over the encapsulating dielectric layer and within the via opening. Openings are then formed within ILD layer, over the array of MTJ stacks and the via opening.

Abstract: This invention presents a novel write line segmentation architecture for writing magnetoresitive random access memories (MRAM). Only the memory cells in a selected segment get a high hard axis field generated by a write line current. Memory cells of deselected segments do not receive this hard axis field. This prevents an undesired state change in particularly sensitive memory cells.

Abstract: This invention presents a novel write line segmentation architecture for writing magnetoresitive random access memories (MRAM). Only the memory cells in a selected segment get a high hard axis field generated by a write line current. Memory cells of deselected segments do not receive this hard axis field. This prevents an undesired state change in particularly sensitive memory cells.