Patents by Inventor Christian Badack
Christian Badack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11650877Abstract: A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.Type: GrantFiled: May 22, 2020Date of Patent: May 16, 2023Assignee: Infineon Technologies AGInventors: Thomas Kern, Klaus Oberlaender, Christian Badack, Michael Goessel
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Patent number: 11556412Abstract: A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.Type: GrantFiled: October 25, 2019Date of Patent: January 17, 2023Assignee: Infineon Technologies AGInventors: Christian Badack, Jessica Trebst, Michael Goessel, Klaus Oberlaender
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Patent number: 11182246Abstract: Systems, methods, and circuitries are disclosed for protecting data throughout read and write operations. In one example a method includes receiving a plurality of data bits; dividing the plurality of data bits into at least two data blocks; generating respective sets of block check bits for each respective data block using a respective first error code; combining the sets of block check bits to generate a set of signature bits for the plurality of data bits; generating a set of cumulative check bits for the plurality of data bits and the set of signature bits using a second error code; and storing, in a memory location, the plurality of data bits, the set of signature bits, and the set of cumulative check bits.Type: GrantFiled: July 28, 2020Date of Patent: November 23, 2021Assignee: Infineon Technologies AGInventors: Thomas Kern, Christian Badack, Michael Goessel, Klaus Oberlaender
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Publication number: 20200371864Abstract: A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.Type: ApplicationFiled: May 22, 2020Publication date: November 26, 2020Inventors: Thomas Kern, Klaus Oberlaender, Christian Badack, Michael Goessel
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Patent number: 10812109Abstract: A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.Type: GrantFiled: November 2, 2018Date of Patent: October 20, 2020Assignee: Infineon Technologies AGInventors: Thomas Kern, Christian Badack, Michael Goessel
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Publication number: 20200133763Abstract: A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.Type: ApplicationFiled: October 25, 2019Publication date: April 30, 2020Inventors: Christian Badack, Jessica Trebst, Michael Goessel, Klaus Oberlaender
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Patent number: 10623026Abstract: A circuit arrangement for determining a correction signal on the basis of at least one bit error of a binary word is specified, including a plurality of subcircuits (ST), wherein a respective subcircuit is provided for a bit position to be corrected of the binary word, wherein each of the subcircuits provides at least two locator polynomial values, and comprising a selection unit, which determines a correction signal depending on the locator polynomial values and depending on an error signal (err, E). A method for driving such a circuit arrangement is furthermore proposed.Type: GrantFiled: October 28, 2016Date of Patent: April 14, 2020Assignee: Infineon Technologies AGInventors: Thomas Kern, Christian Badack, Michael Goessel
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Publication number: 20190132006Abstract: A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.Type: ApplicationFiled: November 2, 2018Publication date: May 2, 2019Inventors: Thomas Kern, Christian Badack, Michael Goessel
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Publication number: 20170126253Abstract: A circuit arrangement for determining a correction signal on the basis of at least one bit error of a binary word is specified, including a plurality of subcircuits (ST), wherein a respective subcircuit is provided for a bit position to be corrected of the binary word, wherein each of the subcircuits provides at least two locator polynomial values, and comprising a selection unit, which determines a correction signal depending on the locator polynomial values and depending on an error signal (err, E). A method for driving such a circuit arrangement is furthermore proposed.Type: ApplicationFiled: October 28, 2016Publication date: May 4, 2017Inventors: Thomas Kern, Christian Badack, Michael Goessel
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Patent number: 9450613Abstract: A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits and a second set of bits is provided. For the first set of bits an error correction of correctable bit errors within the first set is provided by the parity check matrix and for the second set of bits an error detection of a detectable bit errors within the second set is provided by the parity check matrix.Type: GrantFiled: July 10, 2014Date of Patent: September 20, 2016Assignee: Infineon Technologies AGInventors: Thomas Kern, Ulrich Backhausen, Thomas Rabenalt, Michael Goessel, Klaus Oberlaender, Christian Badack
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Patent number: 9362953Abstract: A circuitry for error correction includes a plurality of subcircuits for determining intermediate values Zw0, Zw1, Zw2, Zw3 to be used as coefficients in an error correction expression (z1i, z2i, . . . , zmi)=Zw3·?3ji+Zw2·?2ji+Zw1·?ji+Zw0. The intermediate values Zw0, Zw1, Zw2, Zw3 are determined depending on subsyndromes s1, s3, s5 so that in case of a 1-bit, 2-bit, or 3-bit error zi=(z1i, z2i, . . . , zmi)=(0, 0, . . . , 0) when an error occurred in the bit position i, and zi=(z1i, z2i, . . . , zmi)?(0, 0, . . . , 0) when no error occurred in the bit position i. A correction value ?vi= for the bit position i may then be determined on the basis of the error correction expression evaluated for ?ji.Type: GrantFiled: August 2, 2013Date of Patent: June 7, 2016Assignee: Infineon Technologies AGInventors: Thomas Kern, Michael Goessel, Christian Badack
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Patent number: 9203437Abstract: A circuitry is proposed for the correction of errors in a possibly erroneous binary word v?=v?1, . . . , v?n relative to a codeword v=v1, . . . , vn, in particular 3-bit errors containing an adjacent 2-bit error (burst error). The circuitry comprises a syndrome generator and a decoder. A modified BCH is used wherein n? column vectors of a first BCH code submatrix are paired as column vector pairs so that a componentwise XOR combination of the two column vectors of each column vector pair produces an identical column vector K that is different from all column vectors of the first BCH submatrix. A second BCH submatrix comprises corresponding column vectors as the third power, according to Galois field arithmetic, of the column vector in the first BCH submatrix. The syndrome generated by the syndrome generator can be checked against the columns of the first and second submatrices.Type: GrantFiled: December 19, 2012Date of Patent: December 1, 2015Assignee: Infineon Technologies AGInventors: Thomas Kern, Ulrich Backhausen, Thomas Rabenalt, Christian Badack, Michael Goessel
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Publication number: 20150039976Abstract: A circuitry for error correction includes a plurality of subcircuits for determining intermediate values Zw0, Zw1, Zw2, Zw3 to be used as coefficients in an error correction expression (z1i, z2i, . . . , zmi)=Zw3·?3ji+Zw2·?2ji+Zw1·?ji+Zw0. The intermediate values Zw0, Zw1, Zw2, Zw3 are determined depending on subsyndromes s1, s3, s5 so that in case of a 1-bit, 2-bit, or 3-bit error zi=(z1i, z2i, . . . , zmi)=(0, 0, . . . , 0) when an error occurred in the bit position i, and zi=(z1i, z2i, . . . , zmi)?(0, 0, . . . , 0) when no error occurred in the bit position i. A correction value ?vi= for the bit position i may then be determined on the basis of the error correction expression evaluated for ?ji.Type: ApplicationFiled: August 2, 2013Publication date: February 5, 2015Inventors: Thomas Kern, Michael Goessel, Christian Badack
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Publication number: 20150007001Abstract: A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits and a second set of bits is provided. For the first set of bits an error correction of correctable bit errors within the first set is provided by the parity check matrix and for the second set of bits an error detection of a detectable bit errors within the second set is provided by the parity check matrix.Type: ApplicationFiled: July 10, 2014Publication date: January 1, 2015Inventors: Thomas Kern, Ulrich Backhausen, Thomas Rabenalt, Michael Goessel, Klaus Oberlaender, Christian Badack
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Publication number: 20140173386Abstract: A circuitry is proposed for the correction of errors in a possibly erroneous binary word v?=v?1, . . . , v?n relative to a codeword v=v1, . . . , vn, in particular 3-bit errors containing an adjacent 2-bit error (burst error). The circuitry comprises a syndrome generator and a decoder. A modified BCH is used wherein n? column vectors of a first BCH code submatrix are paired as column vector pairs so that a componentwise XOR combination of the two column vectors of each column vector pair produces an identical column vector K that is different from all column vectors of the first BCH submatrix. A second BCH submatrix comprises corresponding column vectors as the third power, according to Galois field arithmetic, of the column vector in the first BCH submatrix. The syndrome generated by the syndrome generator can be checked against the columns of the first and second submatrices.Type: ApplicationFiled: December 19, 2012Publication date: June 19, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Thomas Kern, Ulrich Backhausen, Thomas Rabenalt, Christian Badack, Michael Goessel